Transistor shield structure, packaged device, and method of manufacture

A transistor comprising:

• a semiconductor substrate having a first terminal and a gate region;
• and
• an interconnect structure on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material, the electrically conductive material including at least a first layer and a second layer spaced apart from the first layer by a first dielectric layer of the dielectric material, the first layer residing closest to the upper surface of the semiconductor substrate relative to the second layer, and the interconnect structure comprising:
• a pillar formed from the electrically conductive material, the pillar being in electrical contact with the first terminal, the pillar extending through the dielectric material, the pillar including a pillar segment in the first layer of the electrically conductive material;
• a first shield structure in the first layer of the electrically conductive material and positioned between the pillar segment and the gate region;
• a tap interconnect formed from the electrically conductive material, the tap interconnect being in electrical contact with the gate region, the tap interconnect extending through the dielectric material;
• and
• a second shield structure formed from the electrically conductive material, the second shield structure being formed in at least the second layer, wherein the second shield structure is not formed in the first layer, and the second shield structure is configured to block an electric field between the tap interconnect and the pillar.

An amplifier module comprising:

• a substrate with a mounting surface;
• and
• a transistor coupled to the mounting surface of the substrate, the transistor including:
• a semiconductor substrate having a first terminal and a gate region;
• an interconnect structure on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material, the electrically conductive material including at least a first layer and a second layer spaced apart from the first layer by a first dielectric layer of the dielectric material, the first layer residing closest to the upper surface of the semiconductor substrate relative to the second layer, and wherein the interconnect structure includes:
• a pillar formed from the electrically conductive material, the pillar being in electrical contact with the first terminal, the pillar extending through the dielectric material, the pillar including a pillar segment in the first layer of the electrically conductive material;
• and
• a shield structure in the first layer of the electrically conductive material and positioned between the pillar segment and the gate region;
• and
• a ground plane formed in the first layer of the interconnect structure, and the shield structure is electrically connected to the ground plane.

An amplifier module comprising:

• a substrate with a mounting surface;
• and
• a transistor coupled to the mounting surface of the substrate, the transistor including:
• a semiconductor substrate having a first terminal and a gate region;
• and
• an interconnect structure on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material, the electrically conductive material including at least a first layer and a second layer spaced apart from the first layer by a first dielectric layer of the dielectric material, the first layer residing closest to the upper surface of the semiconductor substrate relative to the second layer, and wherein the interconnect structure includes:
• a pillar formed from the electrically conductive material, the pillar being in electrical contact with the first terminal, the pillar extending through the dielectric material, the pillar including a pillar segment in the first layer of the electrically conductive material;
• a first shield structure in the first layer of the electrically conductive material and positioned between the pillar segment and the gate region;
• a tap interconnect formed from the electrically conductive material, the tap interconnect being in electrical contact with the gate region, the tap interconnect extending through the dielectric material, and the tap interconnect forming a portion of an input to the gate region;
• and
• a second shield structure formed from the electrically conductive material, the second shield structure being formed in at least the second layer, wherein the second shield structure is not formed in the first layer, the second shield structure is configured to block an electric field between the tap interconnect and the pillar, and the pillar forms a portion of an output from the first terminal.

A method of manufacturing a transistor comprising:

• providing a semiconductor substrate having a first terminal and a gate region;
• and
• forming an interconnect structure on an upper surface of the semiconductor substrate of multiple layers of dielectric material and electrically conductive material, the forming the interconnect structure comprising:
• forming a pillar from the electrically conductive material, the pillar electrically contacting the first terminal, the pillar extending through the dielectric material, wherein the forming the pillar includes forming a first pillar segment in a first layer of the electrically conductive material, the first layer residing closest to the upper surface of the semiconductor substrate without an intervening layer of the electrically conductive material;
• and
• forming a shield structure in the first layer of the electrically conductive material and positioned between the pillar segment and the gate region;
• and
• forming a ground plane in the first layer of the electrically conductive material;
• and forming a connection structure overlapping the gate region, the connection structure interconnecting the shield structure to the ground plane, and the shield structure, connection structure, and ground plane being electrically isolated from the gate region.