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US 10,593,618 B2Granted
Packaged die stacks with stacked capacitors and methods of assembling same
AssigneeIntel Corporation
InventorsBok Eng Cheah, Mooi Ling Chang, Ping Ping Ooi, Jackson Chung Peng Kong, Wen Wei Lum
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Abstract
A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.
Claims7
A semiconductive apparatus, comprising:
- a primary die disposed on a package substrate at a primary package level;
- a subsequent die stacked above the primary die at a subsequent package level;
- a first subsequent-level capacitor located at the subsequent package level, wherein the first subsequent-level capacitor is electrically coupled to the subsequent die;
- a first primary-level capacitor disposed on the package substrate at the primary package level, wherein the first primary-level capacitor is electrically coupled to the primary die;
- a secondary die located at a secondary package level that is stacked above and on the primary package level, and that is located below the subsequent package level;
- a first secondary-level capacitor located at the secondary package level, wherein the first secondary-level capacitor is electrically coupled to the secondary die;
- a subsequent primary-level capacitor disposed on the package substrate at the primary package level, wherein the subsequent primary-level capacitor is electrically coupled to the primary die;
- and
- a subsequent secondary-level capacitor located at the secondary package level, wherein the subsequent secondary-level capacitor is electrically coupled to the secondary die;
- wherein the first primary-level capacitor, and the first subsequent-level capacitor share a merged power rail, wherein the subsequent primary-level capacitor is electrically coupled to the primary die by a dedicated power rail, and wherein the subsequent secondary-level capacitor is electrically coupled to the secondary die by a dedicated power rail.
7 more elements
A semiconductive apparatus, comprising:
- a primary die disposed on a package substrate at a primary package level;
- a subsequent die stacked above the primary die at a subsequent package level;
- a first subsequent-level capacitor located at the subsequent package level, wherein the first subsequent-level capacitor is electrically coupled to the subsequent die;
- and
- a first primary-level capacitor disposed on the package substrate at the primary package level, wherein the first primary-level capacitor is electrically coupled to the primary die;
- wherein the first primary-level capacitor and the first subsequent-level capacitor share a merged power rail.
3 more elements
An assembly process comprising:
- seating a capacitor at a subsequent level of a stacked-die package, wherein a primary die is located at a primary package level that is disposed on a package substrate, and wherein the subsequent level is above the primary package level;
- connecting the capacitor to at least one of the primary die and a subsequent die;
- and
- forming a molding layer that at least partially encapsulates the capacitor and the subsequent die wherein the capacitor is a first tertiary-level capacitor, and wherein the subsequent die is a tertiary die located above and on a secondary package level, further including:
- seating a secondary die above and on the primary die at the secondary package level;
- seating a first secondary-level capacitor above and on the primary package level, and coupling the first secondary-level capacitor to the secondary die by a merged power rail;
- seating a subsequent secondary-level capacitor above an on the primary package level, and coupling the subsequent secondary-level capacitor to the secondary die by a dedicated power rail.
4 more elements
An assembly process comprising:
- seating a capacitor at a subsequent level of a stacked-die package, wherein a primary die is located at a primary package level that is disposed on a package substrate, and wherein the subsequent level is above the primary package level;
- connecting the capacitor to at least one of the primary die and a subsequent die;
- and
- forming a molding layer that at least partially encapsulates the capacitor and the subsequent die, wherein the capacitor is a first quaternary-level capacitor, and wherein the subsequent die is a quaternary die located above and on a tertiary package level, further including:
- seating a secondary die above and on the primary die at a secondary package level;
- seating a first secondary-level capacitor above and on the primary package level, and coupling the first secondary-level capacitor to the secondary die by a merged power rail;
- seating a tertiary die above and on the secondary package level;
- seating a first tertiary-level capacitor above and on the secondary package level, and coupling the first tertiary-level capacitor to the tertiary die by a merged power rail;
- seating a subsequent tertiary-level capacitor above and on the secondary package level, and coupling the subsequent tertiary-level capacitor to the tertiary die by a dedicated power rail.
6 more elements
A computing system, comprising:
- a primary die disposed on a package substrate at a primary package level;
- a subsequent die stacked above the primary die at a subsequent package level;
- a first subsequent-level capacitor located at the subsequent package level, wherein the first subsequent-level capacitor is electrically coupled to the subsequent die;
- and
- a board bonded to the package substrate at an electrical bump array;
- and
- a shell portion of the board, wherein the shell portion electrically insulates the primary die and the board.
4 more elements
Dependencies are inferred from the claim text.