Chip package with sidewall metallization
AssigneeInfineon Technologies AG
InventorsAndre Schmenn, Damian Sojka
Life of this patent
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Abstract
A chip package and manufacturing method is disclosed. In one example, the method includes forming a carrier wafer with a plurality of trenches, each trench being at least partially covered with an electrically conductive sidewall coating. A semiconductor wafer is bonded on a front side of the carrier wafer. An electrically conductive connection structure is formed, including at least partially bridging a gap between the electrically conductive sidewall coating and an integrated circuit element of a respective one of the electronic chips. Material on a backside of the carrier wafer is removed to singularize the bonded wafers at the trenches into a plurality of semiconductor devices.
Claims20
A manufacturing method, comprising:
- forming a carrier wafer with a plurality of trenches, each trench being at least partially covered with an electrically conductive sidewall coating;
- bonding a semiconductor wafer on a front side of the carrier wafer so that each of a plurality of electronic chips of the semiconductor wafer is aligned with respect to a respective one of the trenches;
- forming an electrically conductive connection structure at least partially bridging a gap between the electrically conductive sidewall coating and an integrated circuit element of a respective one of the electronic chips;
- and
- removing material on a backside of the carrier wafer to thereby singularize the bonded wafers at the trenches into a plurality of semiconductor devices.
Dependencies are inferred from the claim text.