Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap
AssigneeInternational Business Machines Corporation
InventorsTakashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan
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Abstract
Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.
Claims12
A method for forming a plurality of semiconductor devices, comprising:
- forming first source and drain regions by implanting a region of a continuous semiconductor substrate formed from a group IV semiconductor material to define a first, p-type channel region in the substrate between the first source and drain regions;
- forming a trench in the continuous semiconductor substrate, the trench being defined on sides and a bottom by the group IV semiconductor material;
- forming a region of III-V semiconductor material embedded in the trench in the continuous semiconductor substrate by completely filling the trench with the III-V semiconductor material, the region of III-V semiconductor material comprising second source and drain regions and a second, n-type channel region between the second source and drain regions;
- forming a silicon cap on the second, n-type channel region after cleaning top surfaces of the first and second channel regions, by masking the first, p-type channel region and depositing silicon with a directional deposition process;
- activating the silicon cap to improve gate dielectric nucleation;
- forming a gate dielectric layer over the silicon cap after activating the silicon cap;
- and
- forming a gate on the gate dielectric.
A method for forming a plurality of semiconductor devices, comprising:
- forming first source and drain regions by implanting a region of a continuous semiconductor substrate formed from a group IV semiconductor material to define a first p-type channel region in the substrate between the first source and drain regions;
- forming a trench in the continuous semiconductor substrate, the trench being defined on sides and a bottom by the group IV semiconductor material;
- forming a region of III-V semiconductor material embedded in the trench in the continuous semiconductor substrate by completely filling the trench with the III-V semiconductor material, the region of III-V semiconductor material comprising second source and drain regions and a second n-type channel region between the second source and drain regions, coplanar with the first p-type channel region;
- forming a silicon cap on one or more of the first and second channel regions after cleaning top surfaces of the first and second channel regions by depositing silicon with a directional deposition process;
- activating the silicon cap to improve gate dielectric nucleation;
- forming a gate dielectric layer over the silicon cap after activating the silicon cap;
- and
- forming a gate on the gate dielectric.
Dependencies are inferred from the claim text.