Vertical FET with various gate lengths by an oxidation process

A method of forming a vertical field effect transistor (VFET) device, the method comprising the steps of:

• patterning fins having a uniform height in a substrate, the fins comprising at least one first fin and at least one second fin;
• forming bottom source and drains at a base of the fins;
• selectively recessing the at least one second fin and the bottom source and drains at the base of the at least one second fin using a low-temperature directional oxidation process such that i) the at least one first fin has a height H1 and the at least one second fin has a height H2, wherein H2>H1, and ii) the bottom source and drains at the base of the at least one first fin has a thickness t1 and the bottom source and drains at the base of the at least one second fin has a thickness t2, wherein t1>t2, and wherein H1+t1=H2+t2;
• forming bottom spacers on the bottom source and drains;
• forming gates above the bottom spacers alongside the fins, wherein the gates alongside the at least one first fin have a first gate length Lg1, wherein the gates alongside the at least one second fin have a second gate length Lg2, and wherein Lg2>Lg1;
• forming top spacers above the gates at tops of the fins;
• and
• forming top source and drains above the top spacers.