Methods of manufacturing a semiconductor device

A method of manufacturing a semiconductor device, the method comprising:

• forming dummy gate structures on a substrate;
• forming a preliminary first interlayer insulation pattern to fill a gap between the dummy gate structures;
• etching an upper portion of the preliminary first interlayer insulation pattern to form a preliminary recess having a round-shaped bottom and a preliminary second interlayer insulation pattern under the preliminary recess through a first etching process;
• implanting an ion on the dummy gate structures and the preliminary second interlayer insulation pattern;
• etching a portion of the preliminary second interlayer insulation pattern through a second etching process to form a recess having a flat bottom and an interlayer insulation pattern under the recess;
• forming a capping pattern on the interlayer insulation pattern;
• and
• replacing the dummy gate structures with gate structures,
• wherein an etching selectivity between silicon oxide and silicon nitride in the second etching process is smaller than an etching selectivity between silicon oxide and silicon nitride in the first etching process.

A method of manufacturing a semiconductor device, the method comprising:

• forming gate structures on a substrate;
• forming a preliminary interlayer insulation pattern including silicon oxide to fill a gap between the gate structures;
• forming a mask pattern on the gate structures and the preliminary interlayer insulation pattern to cover a contact-forming region;
• partially etching an upper portion of the preliminary interlayer insulation pattern using the mask pattern as an etching mask to form a recess and an interlayer insulation pattern under the recess;
• forming a capping pattern including silicon nitride on the interlayer insulation pattern to fill the recess;
• implanting an ion on the gate structures, the interlayer insulation pattern, and the capping pattern so that an etching selectivity between silicon oxide and silicon nitride is increased;
• and
• etching the interlayer insulation pattern doped with an ion to form a contact hole.