Testing content addressable memory and random access memory

A method comprising:

• receiving digital outputs of a content addressable memory (CAM) (CAM match outputs) on first data inputs of a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits;
• addressing a random access memory (RAM) via first outputs of the L1 latch circuits and digital inputs of the RAM (RAM inputs);
• receiving digital outputs (ABIST outputs) of an array built-in self-test (ABIST) controller circuit via a plurality of multiplexer (MUX) circuits, logically coupled to the plurality of L1 latch circuits and via a plurality of exclusive or (XOR) circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, on first scan inputs of the L1 latch circuits;
• outputting compression data (L2 scan out data) via second outputs of the L2 latch circuits;
• providing feedback data via at least two XOR circuits (outer XOR circuits), wherein each of the outer XOR circuits is logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits;
• and
• directing, via a compare mask circuit logically coupled to the CAM, the CAM to output one bit of the CAM match outputs at a time.