Shift register unit and driving method thereof, gate driving circuit
AssigneesBoe Technology Group Co., Ltd., Beijing Boe Optoelectronics Technology Co., Ltd.
InventorsHaifei Su, Shuai Xu
Life of this patent
Estimating the term…
Abstract
The shift register unit includes an input circuit, a first reset circuit, an output circuit, a second reset circuit, and a first pull-down control circuit. The input circuit provides a forward scan control signal to a first node according to an input signal. The first reset circuit provides a reverse scan control signal to the first node according to a reset signal. The output circuit provides a clock signal to a signal output terminal according to the voltage of the first node. The second reset circuit provides a first voltage signal to the first node and the signal output terminal according to the voltage of a second node. The first pull-down control circuit controls the voltage of the second node according to the voltage of the first node.
Claims16
A shift register unit, comprising:
- an input circuit configured to provide a forward scan control signal from a forward scan control signal terminal to a first node according to an input signal from a signal input terminal;
- a first reset circuit configured to provide, according to a reset signal from a reset signal terminal, a reverse scan control signal from a reverse scan control signal terminal to the first node to reset the voltage of the first node;
- an output circuit configured to provide a clock signal from a clock signal terminal to a signal output terminal as an output signal according to the voltage of the first node;
- a second reset circuit configured to provide, according to the voltage of a second node, a first voltage signal from a first voltage signal terminal to the first node and the signal output terminal to reset the voltage of the first node and the output signal;
- and
- a first pull-down control circuit configured to control the voltage of the second node according to the voltage of the first node;
- wherein during forward scanning, the forward scan control signal is an AC voltage signal, and the reverse scan control signal is a DC voltage signal;
- wherein during reverse scanning, the reverse scan control signal is an AC voltage signal, and the forward scan control signal is a DC voltage signal;
- and
- wherein the AC voltage signal and the clock signal have the same frequency and opposite phases.
A shift register unit, comprising:
- a first transistor having a control electrode coupled to a signal input terminal, a first electrode coupled to a forward scan control signal terminal, and a second electrode coupled to a first node;
- a second transistor having a control electrode coupled to a reset signal terminal, a first electrode coupled to a reverse scan control signal terminal, and a second electrode coupled to the first node;
- a third transistor having a control electrode coupled to the first node, a first electrode coupled to a clock signal terminal, and a second electrode coupled to a signal output terminal;
- a first capacitor coupled between the first node and the signal output terminal;
- a fourth transistor having a control electrode coupled to a second node, a first electrode coupled to a first voltage signal terminal, and a second electrode coupled to the first node;
- a fifth transistor having a control electrode coupled to the second node, a first electrode coupled to the first voltage signal terminal, and a second electrode coupled to the signal output terminal;
- a sixth transistor having a control electrode coupled to the first node, a first electrode coupled to the first voltage signal terminal, and a second electrode coupled to the second node;
- a seventh transistor having a first electrode coupled to a second voltage signal terminal, and a second electrode coupled to the second node;
- an eighth transistor having a control electrode coupled to the first node, a first electrode coupled to the first voltage signal terminal, and a second electrode coupled to the control electrode of the seventh transistor;
- and
- a ninth transistor having a control electrode and a first electrode coupled to the second voltage signal terminal, and a second electrode coupled to the control electrode of the seventh transistor,
- wherein during forward scanning, the forward scan control signal is an AC voltage signal, and the reverse scan control signal is a DC voltage signal;
- wherein during reverse scanning, the reverse scan control signal is an AC voltage signal, and the forward scan control signal is a DC voltage signal;
- and
- wherein the AC voltage signal and the clock signal have the same frequency and opposite phases.
Dependencies are inferred from the claim text.