Memory circuit with leakage compensation
AssigneeTexas Instruments Incorporated
InventorsStephen Keith Heinrich-Barna, Raviprakash Suryanarayana Rao
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Abstract
A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.
Claims4
A memory array, comprising:
- a word line lead;
- a control gate lead;
- a bit line lead;
- a first transistor having a first terminal, a second terminal, and a third terminal, the first transistor's first terminal is coupled to the word line lead and the first transistor's second terminal is coupled to the bit line lead;
- a second transistor having a first terminal, a second terminal, and a third terminal, the second transistor's first terminal is coupled to the control gate lead and the second transistor's second terminal is coupled to the first transistor's third terminal.
Dependencies are inferred from the claim text.