Reading circuit and method for a non-volatile memory device

A sense-amplifier circuit comprising:

• a first comparison input;
• a second comparison input;
• a first biasing transistor arranged between a bit line and the first comparison input, the first biasing transistor having a control terminal coupled to a biasing node;
• a second biasing transistor arranged between a reference bit line and the second comparison input, the second biasing transistor having a control terminal coupled to the biasing node;
• a first injection transistor having a first conduction terminal coupled to the first comparison input, a second conduction terminal, and a control terminal coupled to the biasing node;
• a second injection transistor having a first conduction terminal coupled to the second comparison input, a second conduction terminal, and a control terminal coupled to the biasing node;
• a first enabling transistor arranged between a supply voltage node and the second conduction terminal of the first injection transistor, the first enabling transistor having a control terminal coupled to receive a read-enable signal;
• a second enabling transistor arranged between the supply voltage node and the second conduction terminal of the second injection transistor, the second enabling transistor having a control terminal coupled to receive the read-enable signal;
• a first switch element arranged between the supply voltage node and the first comparison input;
• a second switch element arranged between the supply voltage node and the second comparison input;
• a third switch element coupled to the first comparison input and a first output terminal;
• a fourth switch element coupled to the second comparison input and a second output terminal;
• a first latch transistor arranged between the supply voltage node and a first internal node coupled to the third switch element;
• a second latch transistor arranged between the first internal node and a second internal node, the second latch transistor having a control terminal coupled to receive a biasing voltage;
• a third latch transistor arranged between the supply voltage node and a second internal node coupled to the fourth switch element;
• and
• a fourth latch transistor arranged between the second internal node and a second internal node, the second latch transistor having a control terminal coupled to receive the biasing voltage.

A method for reading a non-volatile memory device having a memory array with memory cells arranged in word lines and bit lines and coupled to respective source lines, the method during a reading step of a datum stored in a memory cell comprising:

• receiving a cell current from a bit line associated with the memory cell and a reference current, the reference current from a reference bit line associated with a complementary memory cell in a differential reading operation and from a current-reference generator in a single-ended reading operation;
• generating a first output voltage and a second output voltage that are a function of a difference between the cell current and the reference current;
• and
• causing an injection of current into a source line associated with the memory cell and with the complementary memory cell, the injection current being substantially uniform in the differential and single-ended reading operations.

A method of operating a sense-amplifier circuit, the method comprising:

• during a differential-ended reading operation, receiving a first cell current from a bit line associated with a memory cell;
• during the differential-ended reading operation, receiving a first reference current from a reference bit line associated with a complementary memory cell;
• during the differential-ended reading operation, generating a first output voltage at a first output terminal and a second output voltage at a second output terminal, the first and second output voltages being a function of a difference between the first cell current and the first reference current;
• during a single-ended reading operation, receiving a second cell current from a bit line associated with the memory cell;
• during the single-ended reading operation, receiving a second reference current from a reference current generator;
• during the single-ended reading operation, generating a third output voltage at the first output terminal and a fourth output voltage at the second output terminal, the third and fourth output voltages being a function of a difference between the second cell current and the second reference current;
• and
• causing an injection of current into a source line associated with the memory cell and the complementary memory cell, the injected current being substantially uniform in the differential and in the single-ended reading operations.