Memory device comprising flash memory and method for controlling a write speed of a bus transmitting data for storage on the flash memory

A method for controlling a write speed of a bus transmitting data to a memory device comprising flash memory, the flash memory comprising a plurality of physical blocks, the method comprising:

• (a) setting by a memory device controller of the memory device a cumulative number of physical blocks previously erased from the flash memory to 0 at the beginning of a time interval;
• (b) determining by a memory device controller of the memory device the cumulative number of physical blocks previously erased from the flash memory during the time interval;
• (c) controlling by the memory device controller the write speed of the bus, the write speed of the bus defining a transmission rate at which data are transmitted over the bus from at least one host device to the memory device, the control of the write speed of the bus comprising adapting the transmission rate at which data are transmitted over the bus from the at least one host device to the memory device based on the cumulative number of physical blocks previously erased from the flash memory during the time interval;
• and
• (d) resetting by the memory device controller of the memory device the cumulative number of physical blocks previously erased from the flash memory to 0 at the end of the time interval.

A non-transitory computer program product comprising instructions executable by a memory device controller of a memory device comprising flash memory, the flash memory comprising a plurality of physical blocks, the execution of the instructions by the memory device controller providing for controlling a write speed of a bus transmitting data to the memory device by:

• (a) setting by the memory device controller of the memory device a cumulative number of physical blocks previously erased from the flash memory to 0 at the beginning of a time interval;
• (b) determining by the memory device controller a cumulative number of physical blocks previously erased from the flash memory during the time interval;
• (c)controlling by the memory device controller the write speed of the bus, the write speed of the bus defining a transmission rate at which data are transmitted over the bus from at least one host device to the memory device, the control of the write speed of the bus comprising adapting the transmission rate at which data are transmitted over the bus from the at least one host device to the memory device based on the cumulative number of physical blocks previously erased from the flash memory during the time interval;
• and
• (d) resetting by the memory device controller of the memory device the cumulative number of physical blocks previously erased from the flash memory to 0 at the end of the time interval.