Semiconductor memory device and method of operating the same

A semiconductor memory device comprising:

• a memory cell array including at least one memory block coupled with a plurality of bit lines;
• a peripheral circuit configured to perform a program operation on a plurality of memory cells included in the memory block;
• and
• a control logic configured to control, during a blind program period, the peripheral circuit to apply different program permission voltages determined based on program speeds of the plurality of memory cells, to bit lines coupled to memory cells to be programmed among the plurality of memory cells.

A method of operating a semiconductor memory device, comprising:

• determining, based on positions of bit lines coupled to a memory block selected as a target to be programmed, bit lines disposed adjacent to an address decoder to a first bit line group;
• applying, during a blind program period, a first bit line voltage to a bit line coupled to memory cells to be programmed among the bit lines belonging to the first bit line group, applying a second bit line voltage to a bit line coupled to memory cells to be programmed among bit lines not belonging to the first bit line group, and applying a third bit line voltage to a bit line coupled to memory cells not to be programmed;
• and
• applying a program pulse to a selected word line of the memory block.

A method of operating a semiconductor memory device, comprising:

• providing a first deviation in program speeds between a plurality of memory cells included in a memory block;
• grouping a second plurality of memory cells from the plurality of memory cells to provide a second deviation in program speeds between memory cells in the second plurality of memory cells;
• grouping a third plurality of memory cells from the plurality of memory cells to provide a third deviation in program speeds between memory cells in the third plurality of memory cells;
• applying a first program permission voltage, during a blind program operation of a program operation of the memory block, as a first bit line voltage to bit lines coupled with the second plurality of memory cells;
• and
• applying a second program permission voltage, during the blind program operation of the program operation of the memory block, as a second bit line voltage to bit lines coupled with the third plurality of memory cells,
• wherein a level of the first bit line voltage is different from a level of the second bit line voltage.