Read process in a semiconductor memory device including a memory cell transistor

A semiconductor memory device comprising:

• a word line;
• a first memory cell connected to the word line;
• a first circuit configured to generate a first voltage having a waveform including a first time period during which a voltage value increases with time and a second time period during which the voltage value decreases with time, and apply the generated first voltage to the word line;
• and
• a second circuit configured to measure first time from a first timing when a state of the first memory cell changes according to the first voltage to a second timing when the state of the first memory cell changes according to the first voltage after the first timing, and determine first data stored in the first memory cell on the basis of the measured first time, wherein
• the second circuit includes:
• a first sense amplifier configured to detect the first timing;
• a second sense amplifier configured to detect the second timing;
• a counter circuit configured to measure the first time on the basis of outputs of the first and second sense amplifiers;
• and
• a decode circuit configured to determine the first data on the basis of the measurement result of the counter circuit.