Nonvolatile memory device and operating method thereof

A nonvolatile memory device comprising:

• a plurality of word line drivers configured to drive a plurality of word lines in response to word line enable signals;
• a plurality of write word line drivers configured to driver a plurality of write word lines and the word line enable signals and a write enable signal;
• and
• a plurality of memory cells connected to the plurality of word lines and the plurality of write word lines, respectively,
• wherein each of the plurality of memory cells comprising:
• a variable resistance element;
• and
• a transmission gate connected to the variable resistance element,
• wherein the transmission gate comprising:
• a first insulating layer formed on a well connected to a ground voltage;
• an n-channel metal oxide semiconductor (NMOS) transistor formed on the first insulating layer and connected to one of the plurality of word lines;
• a second insulating layer formed on the well, the second insulating layer being in the same layer as the first insulating layer;
• and
• a p-channel metal oxide semiconductor (PMOS) transistor formed on the second insulating layer and connected to one of the plurality of write word lines.

A nonvolatile memory device comprising:

• a first variable resistance element connected to a first bit line;
• and
• a first transmission gate connected between the first variable resistance element and a first source line,
• wherein the first transmission gate comprises:
• a first insulating layer formed on a well connected to a ground voltage;
• a first n-channel metal oxide semiconductor (NMOS) transistor formed on the first insulating layer and connected to a first word line;
• a second insulating layer formed on the well, the second insulating layer being in the same layer as the first insulating layer;
• and
• a first p-channel metal oxide semiconductor (PMOS) transistor formed on the second insulating layer and connected to a first write word line.