Memory device and signal line layout thereof
AssigneeSK hynix Inc.
InventorsSeung-Gyu Jeong, Kyu-Sung Kim
Life of this patent
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Abstract
A memory device includes a plurality of memory regions including memory cells coupled between a plurality of word lines and a plurality of bit lines, an address decoder suitable for decoding an address to generate a plurality of selection signals corresponding to the bit lines, and outputting the selection signals to a plurality of signal lines, and a plurality of selection circuits corresponding to the memory regions, respectively, and suitable for selecting the bit lines in response to the selection signals received through the signal lines, wherein at least one of the selection circuits is coupled to the signal lines in an arrangement different from remaining selection circuits.
Claims19
A memory device, comprising:
- a plurality of memory regions including memory cells coupled between a plurality of word lines and a plurality of bit lines;
- an address decoder suitable for decoding an address to generate a plurality of selection signals corresponding to the bit lines, and outputting the selection signals to a plurality of signal lines;
- and
- a plurality of selection circuits corresponding to the memory regions, respectively, and suitable for selecting the bit lines in response to the selection signals received through the signal lines,
- wherein at least one of the selection circuits is coupled to the signal lines in an arrangement different from remaining selection circuits, and
- wherein each of the selection circuits receives all the selection signals through the same signal lines.
A memory device, comprising:
- a plurality of memory regions including memory cells coupled between N word lines and N bit lines, where N is a natural number equal to or greater than 3;
- an address decoder suitable for decoding an address to generate first to Nth selection signals corresponding to the bit lines;
- and
- a plurality of selection circuits corresponding to the memory regions, respectively, and suitable for selecting the bit lines in response to the first to Nth selection signals,
- wherein the selection circuits include:
- a first selection circuit suitable for selecting neighboring bit lines among the bit lines in response to first and second selection signals among the first to Nth selection signals;
- and
- a second selection circuit suitable for selecting neighboring bit lines among the bit lines in response to the first selection signal and a (K+1)th selection signal among the first to Nth selection signals, where K is a natural number greater than 1 and equal to or less than N/2−1.
A method of operating a memory device having a plurality of memory regions, the method comprising:
- decoding an address, using an address decoder, to generate a plurality of selection signals respectively corresponding to a plurality of bit lines;
- outputting the selection signals to a plurality of signal lines;
- and
- selecting the bit lines in response to the selection signals received through the signal lines,
- wherein at least one of a plurality of selection circuits, which respectively correspond to the plurality of memory regions, is coupled to the signal lines in an arrangement different from remaining selection circuits,
- wherein each of the selection circuits receives all the selection signals through the same signal lines.
Dependencies are inferred from the claim text.