Row decoding architecture for a phase-change non-volatile memory device and corresponding row decoding method

A non-volatile memory device of the phase-change-memory (PCM) type, the device comprising:

• a memory array comprising a plurality of tiles, each tile of the plurality of tiles having word lines, bit lines, and PCM memory cells coupled to the word lines and the bit lines;
• and
• a row decoder comprising:
• a plurality of main row decoding units, each main row decoding unit of the plurality of main row decoding units coupled to a respective group of tiles of the plurality of tiles;
• and
• a plurality of local row decoding units, each local row decoding unit of the plurality of local row decoding units coupled to a respective tile of the respective group of tiles and configured to carry out local selection and biasing of corresponding word lines based on decoded address signals and bias signals received from a respective main row decoding unit, wherein each local row decoding unit comprises a plurality of logic-combination modules, each logic-combination module of the plurality of logic-combination modules coupled to a respective set of word lines of the respective tile, and wherein each logic-combination module comprises, for each word line of the respective set of word lines:
• a pull-down stage coupled to a respective word line and controlled by respective decoded address signals for selecting the respective word line to bring the respective word line to a reference voltage for a specific combination of the respective decoded address signals;
• and
• a pull-up stage coupled to the respective word line and configured to bring the respective word line to a tile-supply voltage, wherein the pull-up stage is dynamically biased by the respective main row decoding unit in a strong-biasing condition towards the tile-supply voltage, in a non-selected state of the respective word line, or in a weak-biasing condition towards the tile-supply voltage in a selected state of the respective word line, wherein the decoded address signals and the biasing signals are routed from the main row decoding unit to associated local row decoding units coupled to the respective tiles of the respective group of tiles by signal lines, wherein the signal lines extend horizontally from the main row decoding unit, in a direction parallel to the word lines, through the respective group of tiles, in an area distinct from an area occupied by the PCM memory cells of the respective tiles, and wherein, at each tile, the signal lines extend vertically, in a direction parallel to the bit lines, so as to reach local-decoding elements of respective local row decoding unit, the respective local row decoding units arranged on opposite sides of the same tile.

A row decoding method for a non-volatile memory device having a memory array that comprises a plurality of tiles, each tile having word lines and bit lines coupled to memory cells, the method comprising:

• receiving a decoded address signals from a main row decoding unit of the memory array, the main row decoding unit being associated with a group of tiles of the plurality of tiles;
• selecting a local word line of a tile of the group of tiles based on the decoded address signals;
• when the local word line is selected, pulling down the selected local word line to a reference voltage using a respective pull-down stage while simultaneously weakly pulling up the selected local word line to a tile-supply voltage using a respective pull-up stage;
• and
• when the local word line is unselected, strongly pulling up the local word line towards the tile-supply voltage using the respective pull-up stage.