Semiconductor storage device including a controller configured to execute a first write and a second write
AssigneeToshiba Memory Corporation
InventorsMasanobu Shirakawa, Takayuki Akamine
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.
Claims14
A semiconductor storage device comprising:
- first and second memory cells;
- a third memory cell, one end of the third memory cell being connected to one end of the first memory cell;
- a fourth memory cell, one end of the fourth memory cell being connected to one end of the second memory cell;
- a first select transistor connected to another end of the third memory cell;
- a second select transistor connected to another end of the fourth memory cell;
- a first word line connected to each gate of the first and second memory cells;
- a second word line connected to each gate of the first and second memory cells, the second word line being adjacent to the first word line;
- and
- a controller configured to execute a first write and a second write, wherein
- in a write operation, the controller sequentially executes the first write for the third memory cell, the second write for the first memory cell, and the first write for the fourth memory cell.
A semiconductor storage device comprising:
- first to fourth memory cells;
- a fifth memory cell, one end of the fifth memory cell being connected to one end of the first memory cell;
- a sixth memory cell, one end of the sixth memory cell being connected to one end of the second memory cell;
- a seventh memory cell, one end of the seventh memory cell being connected to one end of the third memory cell;
- a eighth memory cell, one end of the eighth memory cell being connected to one end of the fourth memory cell;
- a first select transistor connected to another end of the fifth memory cell;
- a second select transistor connected to another end of the sixth memory cell;
- a third select transistor connected to another end of the seventh memory cell;
- a fourth select transistor connected to another end of the eighth memory cell;
- a first word line connected to each gate of the first to fourth memory cells;
- a second word line connected to each gate of the fifth to eighth memory cells, the second word line being adjacent to the first word line;
- and
- a controller configured to execute a first write and a second write, wherein
- in a write operation, the controller sequentially executes the first write for the first memory cell, the first write for the second memory cell, the first write for the third memory cell, the first write for the fourth memory cell, the first write for the fifth memory cell, and the second write for the first memory cell.
Dependencies are inferred from the claim text.