Back to results
US 10,593,390 B2Granted
Dynamic memory supporting simultaneous refresh and data-access transactions
AssigneeRambus Inc.
InventorsFrederick A. Ware, Richard E. Perego
Life of this patent
Estimating the term…
Abstract
Described are dynamic memory systems that perform overlapping refresh and data access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.
Claims14
A discrete memory controller integrated circuit to communicate with an external, discrete multi-bank memory device integrated circuit, the discrete memory controller integrated circuit comprising:
- memory to store a row-based indication of memory cells that have been refreshed in the discrete multi-bank memory device integrated circuit at least within a current refresh interval;
- data transaction generator to generate a data access transaction for a first bank of the discrete multi-bank memory device integrated circuit;
- a refresh transaction generator to generate refresh transactions of memory cells in the discrete multi-bank memory device integrated circuit while refraining from generating refresh transactions for memory cells that have been refreshed within the current refresh interval, the refresh transactions including a refresh transaction for a second bank of the discrete multi-bank memory device integrated circuit that is not pending a data access transaction;
- a queue to store an indication of banks of the discrete multi-bank memory device integrated circuit subject to pending data access transactions and refresh transactions, the indication including the data access transaction for the first bank of the discrete multi-bank memory device integrated circuit, and the refresh transaction of the second bank of the discrete multi-bank memory device integrated circuit that is not pending the data access transaction, wherein of the pending data access transactions and refresh transactions, the data access transaction for the first bank and the refresh transaction for the second bank are organized by the discrete memory controller integrated circuit such that the refresh transaction for the second bank is executed in the second bank while the data-access transaction for the first bank is executed in the first bank;
- and
- a request interface to transmit memory requests to the discrete multi-bank memory device integrated circuit, the memory requests including bank and row address signals to specify activate operations for the data access transaction for the first bank and the refresh transaction for the second bank.
3 more elements
A method of a discrete memory controller integrated circuit for communicating with an external, discrete multi-bank memory device integrated circuit, comprising:
- storing a row-based indication of memory cells that have been refreshed in the discrete multi-bank memory device integrated circuit at least within a current refresh interval;
- generating a data access transaction for a first bank of the discrete multi-bank memory device integrated circuit;
- generating refresh transactions of memory cells in the discrete multi-bank memory device integrated circuit while refraining from generating refresh transactions for memory cells that have been refreshed within the current refresh interval, the refresh transactions including a refresh transaction for a second bank of the discrete multi-bank memory device integrated circuit that is not pending a data access transaction
- storing an indication of banks of the discrete multi-bank memory device integrated circuit subject to pending data access transactions and refresh transactions, the indication including the data access transaction for the first bank of the discrete multi-bank memory device integrated circuit, and the refresh transaction of the second bank of the discrete multi-bank memory device integrated circuit that is not pending the data access transaction;
- organizing the data access transaction for the first bank and the refresh transaction for the second bank into a memory request such that the refresh transaction for the second bank is executed in the second bank while the data-access transaction for the first bank is executed in the first bank;
- and
- transmitting the memory request to the discrete multi-bank memory device integrated circuit, the memory request including bank and row address signals to specify activate operations for the data access transaction for the first bank and the refresh transaction for the second bank.
4 more elements
A discrete memory controller integrated circuit to communicate with an external, discrete multi-bank memory device integrated circuit, the discrete memory controller integrated circuit comprising:
- a means for storing a row-based indication of memory cells that have been refreshed in the discrete multi-bank memory device integrated circuit at least within a current refresh interval;
- a means for generating a data access transaction for a first bank of the discrete multi-bank memory device integrated circuit;
- a means for generating refresh transactions of memory cells in the discrete multi-bank memory device integrated circuit while refraining from generating refresh transactions for memory cells that have been refreshed within the current refresh interval, the refresh transactions including a refresh transaction for a second bank of the discrete multi-bank memory device integrated circuit that is not pending a data access transaction
- a means for storing an indication of banks of the discrete multi-bank memory device integrated circuit subject to pending data access transactions and refresh transactions, the indication including the data access transaction for the first bank of the discrete multi-bank memory device integrated circuit, and the refresh transaction of the second bank of the discrete multi-bank memory device integrated circuit that is not pending the data access transaction, wherein of the pending data access transactions and refresh transactions, the data access transaction for the first bank and the refresh transaction for the second bank are organized by the discrete memory controller integrated circuit such that the refresh transaction for the second bank is executed in the second bank while the data-access transaction for the first bank is executed in the first bank;
- and
- a means for transmitting memory requests to the discrete multi-bank memory device integrated circuit, the memory requests including bank and row address signals to specify activate operations for the data access transaction for the first bank and the refresh transaction for the second bank.
3 more elements
Dependencies are inferred from the claim text.