Semiconductor memory device and detection clock pattern generating method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsSu Yeon Doo, Seungjun Bae, Sihong Kim, Hosung Song
Life of this patent
Estimating the term…
Abstract
A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.
Claims20
A method of operating a graphic memory system including a graphic processor unit (GPU) and a dynamic random access memory (DRAM) device coupled to the GPU, the DRAM including at least one error detection code pin, the method comprising:
- setting a mode setting control signal of the DRAM into one of a first level or a second level;
- receiving a read command from the GPU by the DRAM;
- outputting read data through a data pin in response to the read command by the DRAM and transmitting the read data to the GPU;
- outputting cyclic redundancy check data during a first time period through a first error detection code pin by the DRAM and transmitting the cyclic redundancy check data to the GPU;
- and
- outputting a first error detection code pattern during a second time period through the first error detection code pin by the DRAM and transmitting the first error detection code pattern to the GPU, and the second time period is different from the first time period,
- wherein the first error detection code pattern is a hold pattern when the mode setting control signal is set into the first level and is a random pattern when the mode setting control signal is set into the second level respectively, and the second level is different from the first level.
A method of operating a dynamic random access memory (DRAM) device including at least one error detection code pin, the method comprising:
- setting a mode setting control signal into one of a first level or a second level;
- receiving a read command from an external device;
- outputting read data in response to the read command through a data pin;
- outputting a cyclic redundancy check data through a first error detection code pin during a first time period;
- and
- outputting a first error detection code pattern through the first error detection code pin during a second time period which is different from the first time period,
- wherein the first error detection code pattern is a random pattern when the mode setting control signal is set into the first level and is a hold pattern when the mode setting control signal is set into the second level respectively, and the second level is different from the first level.
A method of operating a dynamic random access memory (DRAM) device including at least one error detection code pin, the method comprising:
- setting a mode setting control signal into one of a first level or a second level;
- receiving a read command from an external device;
- outputting read data in response to the read command through a data pin;
- outputting a cyclic redundancy check data through a first error detection code pin during a first time period, wherein the cyclic redundancy check data are output later than the read data;
- and outputting a first error detection code pattern through the first error detection code pin during a second time period which is different from the first time period, wherein the first error detection code pattern is a random pattern when the mode setting control signal is set into the first level and is a hold pattern when the mode setting control signal is set into the second level respectively, and the second level is different from the first level.
Dependencies are inferred from the claim text.