Semiconductor devices
AssigneeSK hynix Inc.
InventorWoongrae Kim
Life of this patent
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Abstract
A semiconductor device includes a synthesis signal generation circuit, a column control circuit, and a control signal generation circuit. The synthesis signal generation circuit generates a register synthesis signal in response to first and second read pulses sequentially generated during a read operation. The column control circuit generates any one of a first bank selection signal and a second bank selection signal for respectively selecting a first bank group and a second bank group included in a core circuit in response to the first and second read pulses. The control signal generation circuit generates a control signal for controlling an output operation of a mode register in response to the register synthesis signal.
Claims31
A semiconductor device comprising:
- a synthesis signal generation circuit configured to generate a register synthesis signal in response to a first read pulse and a second read pulse which are sequentially generated during a read operation;
- a column control circuit configured to generate any one of a first bank selection signal and a second bank selection signal for respectively selecting a first bank group and a second bank group of a core circuit in response to the first read pulse and the second read pulse;
- and
- a control signal generation circuit configured to generate a control signal for controlling an output operation of a mode register in response to the register synthesis signal.
A semiconductor device comprising:
- a synthesis signal generation circuit configured to generate a register synthesis signal in response to a read pulse;
- a column control circuit configured to generate any one of a first bank selection signal and a second bank selection signal for respectively selecting a first bank group and a second bank group of a core circuit in response to a write pulse or the read pulse;
- and
- a control signal generation circuit configured to generate a control signal for controlling an output operation of a mode register in response to the register synthesis signal.
Dependencies are inferred from the claim text.