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US 10,593,385 B1Granted
Skew-tolerant timing signal gating
AssigneeRambus Inc.
InventorsNeeraj Purohit, Navin Kumar Mishra, Anirudha Shelke
Life of this patent
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Abstract
A gating signal for masking overhead transitions in a timing signal is generated adaptively based on timing events in the incoming timing signal itself to yield a gating window that opens and closes deterministically with respect to active edges of the timing signal.
Claims20
A method of operation within an integrated-circuit component, the method comprising:
- receiving, via an external timing signal link, a first timing signal having (i) a sequence of data-timing transitions preceded by a first interval and succeeded by a second interval, and (ii) a time-varying phase relative to an internal timing domain of the integrated-circuit component;
- detecting a predetermined level of the first timing signal that precedes the initial one of the data-timing transitions and asserting a gate signal in response;
- and
- deasserting the gate signal at a deterministic time relative to a final one of the data-timing transitions, despite the time-varying phase of the first timing signal relative to the internal timing domain of the integrated-circuit component.
1 more element
An integrated-circuit component comprising:
- a timing signal input to receive, via an external timing signal link, a first timing signal having (i) a sequence of data-timing transitions preceded by a first interval and succeeded by a second interval, and (ii) a time-varying phase relative to an internal timing domain of the integrated-circuit component;
- gating circuitry to:
- detect a predetermined level of the first timing signal that precedes the initial one of the data-timing transitions and assert a gate signal in response;
- and
- deassert the gate signal at a deterministic time relative to a final one of the data-timing transitions, despite the time-varying phase of the first timing signal relative to the internal timing domain of the integrated-circuit component.
2 more elements
An integrated circuit component comprising:
- a timing signal input to receive, via an external timing signal link, a first timing signal having (i) a sequence of data-timing transitions preceded by a first interval and succeeded by a second interval, and (ii) a time-varying phase relative to an internal timing domain of the integrated-circuit component;
- means for detecting a predetermined level of the first timing signal that precedes the initial one of the data-timing transitions and asserting a gate signal in response;
- and
- means for deasserting the gate signal at a deterministic time relative to a final one of the data-timing transitions, despite the time-varying phase of the first timing signal relative to the internal timing domain of the integrated-circuit component.
1 more element
Dependencies are inferred from the claim text.