System-level timing budget improvements
AssigneeMicron Technology, Inc.
InventorKang-Yong Kim
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for system-level timing budget are described. Each memory die in a memory device may determine an offset between its system clock signal and its data clock signal. The offsets of each memory die in the memory device may be different; e.g., having different magnitudes and/or polarities. A memory die in the memory device may adjust its own data clock signal by a delay that is based on the offsets of two or more memory die in the device. The memory die may adjust its data clock signal by setting a fuse in a delay adjuster on the memory die. Adjusting the data clock signal may match an offset of a first memory die with an offset of a second memory die.
Claims25
An apparatus, comprising:
- a first memory die configured to receive a first system clock signal and a first data clock signal;
- a second memory die configured to receive a second system clock signal and a second data clock signal;
- and
- a first delay adjuster coupled with the first data clock signal and configured to adjust the first data clock signal by a first delay based at least in part on a first offset between the first system clock signal and the first data clock signal and a second offset between the second system clock signal and the second data clock signal.
A method, comprising:
- receiving, by a first memory die, a first data clock signal and a first system clock signal;
- receiving, by a second memory die, a second data clock signal and a second system clock signal;
- routing, by the first memory die, a third data clock signal and the first system clock signal to a first phase detector, the third data clock signal being offset from the first data clock signal by a first delay;
- routing, by the second memory die, the second data clock signal and the second system clock signal to a second phase detector;
- and
- transmitting, to a memory controller, an indication of a timing adjustment for the first system clock signal, the timing adjustment based at least in part on a first offset between the third data clock signal and the first system clock signal and a second offset between the second data clock signal and the second system clock signal.
A method, comprising:
- transmitting, to a memory controller, an indication of a first offset between a first data clock signal and a first system clock signal, the first offset associated with a first memory die;
- transmitting, to the memory controller, an indication of a second offset between a second data clock signal and a second system clock signal, the second offset associated with a second memory die;
- receiving, from the memory controller, an indication of a first delay, the first delay based at least in part on the first offset and the second offset;
- and
- adjusting the first data clock signal by the first delay.
A method, comprising:
- routing, to a first memory die, a first data clock signal and a first system clock signal;
- routing, to a second memory die, a second data clock signal and a second system clock signal;
- determining a first offset between the first system clock signal and the first data clock signal;
- determining a second offset between the second system clock signal and the second data clock signal;
- selecting a first fuse of a first plurality of fuses of the first memory die based at least in part on the first offset and the second offset;
- and
- adjusting the first data clock signal by a first delay by setting the first fuse.
Dependencies are inferred from the claim text.