Memory systems and devices that support clock-to-clock alignment, training and methods of operating same

A method of operating a memory device configured to perform first training comprising a plurality of loop operations to align a main clock signal and a data clock signal, which are received from a memory controller, the method comprising generating division ratio information indicating a division ratio set based on a frequency ratio of the main clock signal to the data clock signal and transmitting the division ratio information to the memory controller to perform the first training,

• wherein a first loop operation of the loop operations comprises:
• receiving first phase control information from the memory controller, the first phase control information being generated based on the division ratio information;
• dividing the data clock signal based on the division ratio to generate a division data clock signal, selecting a first phase from among a plurality of phases based on the first phase control information, and generating a first comparison target clock signal, the first comparison target clock signal being shifted from the division data clock signal by the first phase;
• and
• comparing a phase of the first comparison target clock signal with a phase of the main clock signal and transmitting a first phase comparison result to the memory controller.