Memory controller with staggered request signal output
AssigneeRambus Inc.
InventorsIan P. Shaeffer, Bret Stott, Benedict C. Lau
Life of this patent
Estimating the term…
Abstract
A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
Claims20
A method of operation in a memory controller integrated circuit (IC) chip, the method comprising:
- during an initialization mode of operation,
- receiving information from an off-chip serial presence detect (SPD) device;
- and
- during a memory device access mode of operation,
- transmitting a control signal to the memory device, the control signal comprising a first component of a memory access request,
- transmitting a command/address (C/A) signal to the memory device after a delay with respect to transmitting the control signal, wherein the delay is based on the information, the C/A signal comprising a second component of the memory access request.
A memory controller integrated circuit (IC) chip, comprising:
- interface circuitry to receive information from an off-chip serial presence detect (SPD) device during an initialization mode of operation;
- timing circuitry to set a transmit delay based on the information;
- request logic to generate a memory access request during a memory access mode of operation, the memory access request including a control signal and a command/address (C/A) signal;
- a first transmitter to transmit the control signal to a memory device;
- a second transmitter to transmit the C/A signal to the memory device with a delay with respect to the control signal, wherein the delay is based on the information.
An integrated circuit (IC) chip comprising:
- memory control circuitry including
- interface circuitry to receive information from an off-chip serial presence detect (SPD) device during an initialization mode of operation;
- timing circuitry to set a transmit delay based on the information;
- request logic to generate a memory access request during a memory access mode of operation, the memory access request including a control signal and a command/address (C/A) signal;
- a first transmitter to transmit the control signal to a memory device;
- a second transmitter to transmit the command/address (C/A) signal to the memory device with a delay with respect to the control signal, wherein the delay is based on the information.
Dependencies are inferred from the claim text.