Memory device

A high bandwidth memory (HBM) device comprising:

• a direct access (DA) interface comprising a plurality of data pads;
• a data distribution circuit suitable for distributing data received through some data pads of the plurality of data pads to an A data bus, and distributing data received through other data pads to a B data bus, in a first mode;
• and
• first to Mth channel regions,
• wherein each of the first to Mth channel regions comprises:
• a pseudo A channel region suitable for storing data obtained by copying the data of the A data bus at a predetermined ratio of 1:N where N is an integer equal to or more than 2;
• and
• a pseudo B channel region suitable for storing data obtained by copying the data of the B data bus at the predetermined ratio of 1:N.

A memory device comprising:

• an interface including a data pad configured to receive first data having a first size;
• a plurality of channel regions, each channel region including a first region and a second region configured to store second data having a second size greater than the first size;
• a data distribution circuit configured to receive the first data from the interface, and transfer the first data or the inverted first data as a first bus data and a second bus data to a first data bus and a second data bus, respectively;
• a first copy circuit configured to receive and copy the first bus data to output the copied first bus data to the first region of each of the plurality of channel regions;
• and
• a second copy circuit configured to receive and copy the second bus data to output the copied second bus data to the second region of each of the plurality of channel regions.