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US 10,593,377 B2Granted
Multiple endianness compatibility
AssigneeMicron Technology, Inc.
InventorsKyle B. Wheeler, Timothy P. Finkbeiner, Jeremiah J. Willcock
Life of this patent
Estimating the term…
Abstract
Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of bytes in a non-bit-sequential format. The method includes reordering the bits in each byte of the plurality of bytes such that the plurality of bytes are arranged in a bit-sequential format.
Claims20
A method, comprising:
- receiving a plurality of bytes in a little-endian bytewise, big-endian bitwise format such that the plurality of bytes are in a sequential format and the bits in each byte of the plurality of bytes are in a non-bit-sequential format;
- and
- reordering, using reordering circuitry comprising multiplexers, the bits in each byte of the plurality of bytes on a bytewise basis, without regard to a number of the bytes of the plurality of bytes and as each byte is received from a processor, such that the bits in each byte of the plurality of bytes are arranged in a bit-sequential format.
A method, comprising:
- receiving, at reordering circuitry, a plurality of bytes in a bytewise little endian bitwise big endian format such that the plurality of bytes are in a sequential format and the bits in each byte of the plurality of bytes are in a non-bit-sequential format, wherein the reordering circuitry comprises an engine within a controller of a memory device;
- and
- using the reordering circuitry to reorder the plurality of bytes on a bytewise basis, without regard to a number of the bytes of the plurality of bytes and as each byte is received from a processor, into a bit-sequential little endian format.
A system comprising:
- a host configured to send bits of a plurality of bytes in a bytewise little endian, bitwise big endian format such that the corresponding bits in each byte are in a non-sequential format;
- a memory device comprising reordering circuitry, wherein the memory device is configured to receive the bits of the plurality of bytes and reorder the bits to a bytewise little endian, bitwise little endian format, without regard to a number of the bytes of the plurality of bytes and as each byte is received by the memory device, using multiplexers of the reordering circuitry;
- wherein the corresponding reordered bits in each byte are in a sequential format on a bytewise basis and without regard to a number of bytes of the plurality of bytes.
Dependencies are inferred from the claim text.