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US 10,593,375 B2Granted
Semiconductor memory device with correcting resistances in series with memory array signal lines
AssigneeToshiba Memory Corporation
InventorKazuyo Ishii
Life of this patent
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Abstract
According to one embodiment, a semiconductor storage device comprises a first memory cell including a first resistance change element; a first bit line and a first source line coupled to the first memory cell; and a first resistance coupled to at least one of the first bit line and the first source line.
Claims13
A semiconductor storage device comprising:
- a first memory cell including a first resistance change element;
- a second memory cell including a second resistance change element;
- a first column selection transistor;
- a second column selection transistor;
- a first bit line coupled between a first terminal of the first memory cell and a first terminal of the first column selection transistor, and between a first terminal of the second memory cell and the first terminal of the first column selection transistor;
- a first source line coupled between a second terminal of the first memory cell and a first terminal of the second column selection transistor, and between a second terminal of the second memory cell and the first terminal of the second column selection transistor;
- and
- a first correcting resistance coupled in series between the first column selection transistor and the second column selection transistor,
- wherein the first memory cell and the second memory cell are coupled in parallel to the first correcting resistance.
6 more elements
A semiconductor storage device comprising:
- a first memory cell including a first resistance change element;
- a second memory cell including a second resistance change element;
- a first column selection transistor;
- a second column selection transistor;
- a first bit line coupled between a first terminal of the first memory cell and a first terminal of the first column selection transistor, and between a first terminal of the second memory cell and the first terminal of the first column selection transistor;
- a first source line coupled between a second terminal of the first memory cell and a first terminal of the second column selection transistor, and between a second terminal of the second memory cell and the first terminal of the second column selection transistor;
- and
- a first variable resistance circuit coupled in series between the first column selection transistor and the second column selection transistor,
- wherein the first memory cell and the second memory cell are coupled in parallel to the first variable resistance circuit.
6 more elements
A semiconductor storage device comprising:
- a first memory cell including a first resistance change element and a first transistor;
- a first word line coupled to a control terminal of the first transistor;
- and
- a first correcting resistance coupled to the first word line,
- wherein the first correcting resistance includes a first terminal coupled to the first memory cell and a second terminal coupled to a row decoder.
2 more elements
Dependencies are inferred from the claim text.