Memory module

A memory module comprising:

• a front side interface configured to include a first command/address receiving unit that receives an address and a command from a host memory controller, a first data transmitting/receiving unit that transmits/receives data to/from the host memory controller, a first clock receiving unit that receives a host clock from the host memory controller, and a first serializer/deserializer that serial-to-parallel converts the command and address received from the first command/address receiving unit, based on the host clock received from the first clock receiving unit, to transfer the converted command, address, and data to a processing block, and parallel-to-serial converts data transferred from the processing block to transfer the converted data to the first data transmitting/receiving unit;
• the processing block configured to operate in synchronization with a division clock, and include a control signal processing block that processes the command and address transferred from the front side interface, and transfer the processed command and address to a back side interface, and a data processing block that generates an error correction code by using the data transferred from the front side interface, and corrects an error of data transferred from the back side interface by using an error correction code transferred from the back side interface;
• the back side interface configured to include a phase locked loop that generates a media clock having a frequency different from a frequency of the host clock, a second serializer/deserializer that parallel-to-serial converts the command, address, data, and error correction code transferred from the processing block, based on the media clock, and serial-to-parallel converts data and an error correction code transferred from one or more memory devices, a command/address transmitting unit that transmits the command and address transferred from the second serializer/deserializer, a second data transmitting/receiving unit that transmits/receives the data and the error correction code between the second serializer/deserializer and the one or more memory devices, and a clock transmitting unit that transmits the media clock;
• and
• the one or more memory devices configured to operate in synchronization with the media clock,
• wherein each of the one or more memory devices comprises:
• a second clock receiving unit configured to receive the media clock transferred from the clock transmitting unit;
• a second command/address receiving unit configured to receive the command and address transferred from the command/address transmitting unit;
• and
• a third data transmitting/receiving unit configured to transmit/receive the data and the error correction code to/from the second data transmitting/receiving unit.