Back to results
US 10,593,304 B2Granted
Signal supply circuit and display device
AssigneeJapan Display Inc.
InventorTakayuki Nakao
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a signal supply circuit used for a display device includes a plurality of subpixels each including a memory. The signal supply circuit includes a first mode. The first mode receives first video data in a unit of n bits corresponding to the subpixels from outside, and supplies digital data for the subpixels in a unit of m bits less than n bits to the subpixels based on the first video data.
Claims14
A signal supply circuit used for a display panel comprising a plurality of subpixels each comprising a memory, the signal supply circuit comprising:
- a latch circuit receiving a serial data as a first video data, a register circuit outputting a latch pulse to the latch circuit, a parallel conversion circuit converting the serial data latched by the latch circuit to a parallel digital data, an allocation circuit allocating the parallel digital data to each of the subpixels, and an input adaptive control circuit receiving identification information of the display panel from outside the display panel, wherein in a first mode, the register circuit outputs n cyclic latch pulses to the latch circuit for receiving the first video data in a unit of n bits from outside the display panel, when a unit of m bits corresponds to the subpixels in the first mode, the allocation circuit cuts parallel digital data that does not correspond to the subpixels and supplies parallel digital data for the unit of m bits corresponding to the subpixels based on the identification information from the input adaptive control circuit, and wherein n>m.
A display device comprising:
- a plurality of subpixels arranged on a display area of a display panel and each comprising a memory;
- a serial data processing circuit arranged on the display panel and which is supplied with serial data, applies parallel conversion to serial video data included in the serial data, and outputs parallel video data;
- a data conversion circuit which obtains the output parallel video data by latching the parallel video data and allocating the latched data to corresponding subpixels of the display panel in an allocation process;
- and
- an input adaptive control circuit which controls the parallel conversion operation of the serial data processing circuit and latch timing and a form of the allocation process of the data conversion circuit in accordance with type information of a layout of the subpixels of the display panel and a mode of the serial video data included in the serial data,
- wherein the serial data processing circuit comprises register circuits and latch circuits,
- the register circuits circulate at least a cyclic latch pulse,
- a number of the cyclic latch pulse is determined in accordance with the mode of the serial video data,
- the latch circuits output the parallel video data to the data conversion circuit based on each latch cyclic latch pulse from the register circuits,
- the data conversion circuit comprises an allocation circuit,
- the allocation circuit changes and outputs the output parallel video data in accordance with the type information of the layout of the subpixels of the display panel and a mode table of the serial video data included in the serial data, and
- the mode table indicates that the mode of the serial video data is one of:
- a 4 bit-data mode, a 3 bit-data mode, a 1 bit-data mode.
10 more elements
Dependencies are inferred from the claim text.