Computer-implemented method for reducing video latency of a computer video processing system and computer program product thereto

A computer program product on a non-transitory media for reducing video latency of a computer video processing system comprising at least one video input source, at least one processor, at least one memory including a computer program code, at least one video input card, at least one graphics processing unit known as GPU and at least one video output display, the computer program product comprising:

• a computer readable code for creating an input thread and an output thread by the at least one processor;
• a computer readable code for configuring the input thread and the output thread to run simultaneously and independently from each other by the at least one processor;
• a computer readable code for choosing a manner of splitting at least one video input frame received from the at least one video input source via the at least one video input card into a plurality of input slices from Si1 to Sin where a single input slice is known as Six by the at least one processor on the input thread;
• and
• a computer readable code for choosing a manner of splitting at least one video output frame into a plurality of output slices from SO1 to SOn where a single output slice is known as Sox via the at least one GPU by the at least one processor on the output thread,
• wherein the computer program product further comprises
• a computer readable code for calculating a start time and an end time for each single input slice Six of the input slices Si1 to Sin of the at least one input frame received from the at least one video input card by the at least one processor on the input thread,
• a computer readable code for locating vertical blanking interval for the at least one video input card by the at least one processor on the input thread,
• a computer readable code for receiving at least one single input slice Six of the plurality of input slices from Si1 to Sin from the at least one video input source via the at least one video input card by the at least one processor until all input slices from Si1 to Sin have been received on the input thread,
• a computer readable code for sending the received at least one single input slice Six to the output thread by the at least one processor until all input slices from Si1 to Sin have been sent to the output thread on the input thread,
• a computer readable code for calculating a start time and an end time for each output slice Sox of SO1 to SOn for the at least one GPU by the at least one processor on the output thread,
• a computer readable code for configuring the at least one GPU to draw directly to a front buffer by the at least one processor on the output thread,
• a computer readable code for calculating a required latency on the basis of positioning the at least one video input frame within the at least one video output frame by the at least one processor on the output thread,
• a computer readable code for locating vertical blanking interval for the at least GPU by the at least one processor on the output thread,
• a computer readable code for receiving the at least one single input slice Six of the input slices Si1 to Sin sent from the input thread by the at least one processor on the output thread,
• a computer readable code for calculating a required at least one input slice Siy, wherein y is from 1 to n, comprising at least one of the input slices from Si1 to Sin for drawing output slices SO1 to SOn for the at least one GPU by the at least one processor on the basis of positioning of the at least one video input frame within the at least one video output frame on the output thread,
• a computer readable code for waiting until the input thread has received all the plurality of input slices from Si1 to Sin from the at least one video input card by the at least one processor on the output thread, and
• a computer readable code for drawing by the at least one processor the required input slices Si1 to Sin for the output slices Soi to Son for the at least one GPU where a single output slice So(x+1) consisting of the required input slices from Si1 to Sin is drawn before the at least one GPU completes sending a single output slice Sox of output slices from SO1 to SOn corresponding to the required at least one input slice Siy to the at least one video output display until the last output slice Son corresponding to the required at least one input slice Siy is sent by the at least one GPU to the at least one video output display on the output thread.