Shift register, gate driving circuit, display panel and driving method

A shift register, comprising:

• an input and set circuit, connected with a pull-up node and configured to:
• in an input stage of forward scanning or a set stage of reverse scanning, receive a first clock signal and a first input signal, and in response to the first clock signal, write a voltage of the first input signal into the pull-up node;
• a storage circuit, connected with the pull-up node and an output end respectively;
• an output circuit, configured to provide a second clock signal to the output end when a voltage of the pull-up node satisfies an output condition;
• a first pull-down circuit, configured to provide a first power voltage to the output end when a first pull-down condition is satisfied, and
• a second pull-down circuit, configured to provide the first power voltage to the output end when a second pull-down condition is satisfied,
• wherein the input and set circuit is further configured to:
• in a set stage of forward scanning or an input stage of reverse scanning, receive a third clock signal and a second input signal, and in response to the third clock signal, write a voltage of the second input signal into the pull-up node;
• wherein the second pull-down circuit includes a seventh transistor, an eighth transistor and a third capacitor,
• a first electrode of the seventh transistor is connected with the first power supply end to receive the first power voltage, a second electrode of the seventh transistor is connected with the output end, and a gate electrode of the seventh transistor is connected with a second pull-down node;
• a first electrode of the eighth transistor is connected with the first power supply end to receive the first power voltage, a second electrode of the eighth transistor is connected with the second pull-down node, and a gate electrode of the eighth transistor is connected with the pull-up node;
• and
• a first end of the third capacitor is connected with a fourth clock signal end to receive the fourth clock signal, and a second end of the third capacitor is connected with the second pull-down node,
• wherein the output circuit includes a first transistor, a first electrode of the first transistor is configured to receive the second clock signal, a second electrode of the first transistor is connected with the output end, and a gate electrode of the first transistor is connected with the pull-up node,
• wherein the storage circuit includes a first capacitor, a first end of the first capacitor is connected with the pull-up node, and a second end of the first capacitor is connected with the output end.