Shift register unit and method for driving same, shift register circuit and display apparatus

A shift register unit, comprising:

• a charging module having an input terminal and a control terminal both connected to an input terminal of the shift register unit and an output terminal connected to a pull-up node, and configured to receive an input signal and pull up a potential at the pull-up node in response to the input signal to generate a pull-up signal;
• a pull-up module having a control terminal connected to the pull-up node, an input terminal connected to a first clock signal terminal of the shift register unit and an output terminal connected to an output terminal of the shift register unit, and configured to receive a first clock signal and charge the output terminal of the shift register unit during a pull-up period in response to the pull-up signal;
• a first pull-down control module having a first control terminal and a first input terminal connected both to a second clock signal terminal of the shift register unit, a second control terminal connected to the pull-up node, a second input terminal connected to a low voltage terminal of the shift register unit and an output terminal connected to a pull-down control node, and configured to receive a second clock signal, and generate a pull-down control signal at the pull-down control node in response to the second clock signal;
• a second pull-down control module having a first control terminal connected to the pull-down control node, a second control terminal connected to the pull-up node, a first input terminal connected to the second clock signal terminal of the shift register unit, a second input terminal connected to the low voltage terminal of the shift register unit and an output terminal connected to a pull-down node, and configured to receive the second clock signal and generate a pull-down signal at the pull-down node in response to the pull-down control signal and the pull-up signal;
• a first pull-down module having a control terminal connected to a first reset terminal of the shift register unit, an input terminal connected to the output terminal of the shift register unit and an output terminal connected to the low voltage terminal of the shift register unit, and configured to discharge the output terminal of the shift register unit in response to a first reset signal in a first pull-down period;
• a second pull-down module having a first control terminal connected to the pull-down node, a second control terminal connected to the second clock signal terminal of the shift register unit, a first input terminal connected to the output terminal of the shift register unit, a second input terminal connected to the pull-up node and an output terminal connected to the low voltage terminal of the shift register unit, and configured to discharge the output terminal of the shift register unit in response to the pull-down signal and the second clock signal in a second pull-down period;
• and
• a reset module having a control terminal connected to a second reset terminal of the shift register unit, an input terminal connected to the pull-up node and an output terminal connected to the low voltage terminal of the shift register unit, and configured to reset the pull-up node in response to a second reset signal in the second pull-down period,
• wherein the first and second clock signals have opposite phases, the second pull-down module is configured to be disabled in the first pull-down period, and the pull-up module is configured to discharge the output terminal of the shift register unit in the first pull-down period,
• wherein the first pull-down control module comprises:
• a seventh transistor having a gate connected to the gate of a third transistor of the pull-up module, a first electrode connected to the pull-down control node and a second electrode connected to the low voltage terminal;
• and an eighth transistor having a gate and a first electrode both connected to the second clock signal terminal and a second electrode connected to the pull-down control node,
• wherein the seventh transistor and the eighth transistor are selected so that the first pull-down control-module maintains a potential at the pull-down control node at low it response to both the second clock signal and the pull-up signal being high in the first pull-down period, and pulls up the potential at the pull-down control node in response to the second clock signal being high and the pull-up signal being low in the second pull-down period.