Display device, gate driving circuit and gate driving unit

A gate driving unit, comprising:

• a signal maintenance circuit which is configured to, during a period that a first clock signal input end of the signal maintenance circuit receives a first clock signal at a high level, output a high level from an output end of the signal maintenance circuit in accordance with a trigger signal at a high level inputted into a trigger signal input end of the signal maintenance circuit;
• a first-level output circuit, wherein a trigger signal input end of the first-level output circuit is connected to the output end of the signal maintenance circuit, and the first-level output circuit is configured to, during a period that a second clock signal input end of first-level output circuit receives a second clock signal at a high level, output a first-level driving signal at a high level from an output end of the first-level output circuit in accordance with the high level from the output end of the signal maintenance circuit;
• and
• a second-level output circuit, wherein a trigger signal input end of the second-level output circuit is connected to the output end of the first-level output circuit, and the second-level output circuit is configured to, during a period that a third clock signal input end of the second-level output circuit receives a third clock signal at a high level, output a second-level driving signal at a high level from an output end of the second-level output circuit in accordance with the high level from the output end of the first-level output circuit,
• wherein the second clock signal at the high level arrives upon the first clock signal at the high level ending, and the third clock signal at the high level arrives upon the second clock signal at the high level ending;
• wherein each of the first-level output circuit and the second-level output circuit further comprises a respective resetting signal input end and is configured to, when the respective resetting signal input end receives a resetting signal, reset the respective output end to be at a low level;
• wherein the resetting signal input end of the first-level output circuit is connected directly to the signal maintenance circuit, and the output end of the first-level output circuit is being reset under the control of a first resetting signal;
• and
• wherein the resetting signal input end of the second-level output circuit receives a second resetting signal, and the second resetting signal is the first clock signal.