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US 10,593,008 B2Granted
Hardware-adaptable watermark systems
AssigneeDigimarc Corporation
InventorsJacob L. Boles, Ravi K. Sharma, John D. Lord
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AssigneeDigimarc Corporation
InventorsJacob L. Boles, Ravi K. Sharma, John D. Lord
Estimating the term…
There are many advantages to implementing a watermark-based system using dedicated hardware, rather than using software executing on a general purpose processor. These include higher speed and lower power consumption. However, hardware implementations incur substantial design and development costs. Moreover, because each watermarking application has its own design constraints and parameters, it has not been cost-effective to develop a hardware chip design for each, since such chips would typically not be manufactured in volumes sufficient to bring per-unit costs down to an acceptable level. The present technology provides various techniques for making watermarking hardware adaptable, so that a single chip can serve multiple diverse watermark applications. By so-doing, the advantages of hardware implementation are made available where it was formerly cost-prohibitive, thereby enhancing operation of a great variety of watermark-based systems.
In silicon circuitry, designed and fabricated for use in decoding watermarked data from imagery, the circuitry including a memory and a pipeline comprising plural hardware modules that are serially coupled, the modules each being configured to process data and transfer processed results to a next module of the pipeline or to a data output, the modules collectively defining an image standardization stage, followed by a synchronization stage, one or more modules of the image standardization stage including a corresponding register set that stores data configuring the image standardization stage to transform input image data into a form expected by the synchronization stage, said register set(s) being connected by a bus to a register control circuit that is configured to write data into said register set(s) based on a configuration file or based on data held in the memory, the synchronization stage including plural modules from the list:
First and second hardware circuits designed and fabricated to serve as digital watermark decoders, characterized in that the first hardware circuit is capable of extracting watermark payload data encoded into a first signal, whereas the second hardware circuit is not capable of extracting watermark payload data encoded into the first signal, and the second hardware circuit is capable of extracting watermark payload data encoded into a second signal, whereas the first hardware circuit is not capable of extracting watermark payload data encoded into the second signal, said two hardware circuits being two instances of the same circuit, a difference between capabilities of the two circuits comprising data stored in registers of one or more modules of said first and second hardware circuits, said register data defining spreading signals used by said first and second hardware circuits in decoding the payload data, or defining embedding locations used by said first and second hardware circuits in decoding the payload data, or defining watermark block size used by said first and second hardware circuits in decoding the payload data, or defining an error correction protocol used by said first and second hardware circuits in decoding the payload data, or defining a pattern of reference signal spatial frequencies used by said first and second hardware circuits in decoding the payload data.
A method employing a first watermark decoding hardware circuit, there being a second watermark decoding circuit that is identical to the first watermark decoding hardware circuit, the second watermark decoding hardware circuit being capable of extracting watermark payload data encoded into a first signal, both of said first and second watermark decoding hardware circuits including pipelined modules drawn from the set:
Dependencies are inferred from the claim text.