Automatic design flow from schematic to layout for superconducting multi-qubit systems

A system for generating a layout for a multi-qubit chip, the system comprising:

• a computer processor, a computer-readable storage medium, and program instructions stored on the computer-readable storage medium being executable by the processor, to cause the computer system to perform a method, comprising:
• receiving, by a computer, a schematic input, wherein the schematic input includes a plurality of qubits, a plurality of coupling busses, a plurality of readout busses, and a plurality of readout ports;
• selecting, by the computer, a qubit design from a qubit library, based on a qubit style in the schematic input;
• selecting, by the computer, a coupling bus style from a bus information library, based on a bus design parameter that specifies a coupling bus frequency;
• generating, by the computer, a coupling bus length, based on the specified coupling bus frequency;
• and
• generating, by the schematic layout program, an initial floor plan qubit layout by assembling the selected coupling bus style, selected qubit design, and the plurality of readout busses and the plurality of readout ports from the input schematic.

A computer program product for generating a layout for a multi-qubit chip, the computer program product comprising a computer readable tangible storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to perform a method, comprising:

• receiving, by a computer, a schematic input, wherein the schematic input includes a plurality of qubits, a plurality of coupling busses, a plurality of readout busses, and a plurality of readout ports;
• selecting, by the computer, a qubit design from a qubit library, based on a qubit style in the schematic input;
• selecting, by the computer, a coupling bus style from a bus information library, based on a bus design parameter that specifies the coupling bus frequency;
• generating, by the computer, a coupling bus length, based on the specified coupling bus frequency;
• and
• generating, by the computer, an initial floor plan qubit layout by assembling the selected coupling bus style, selected qubit design, and the plurality of readout busses and the plurality of readout ports from the input schematic.