Method and system for processing verification tests for testing a design under test
AssigneeCadence Design Systems, Inc.
InventorMeir Ovadia
Life of this patent
Estimating the term…
Abstract
A method for processing verification tests for testing a design under test (DUT), may include receiving from a user a start time message and an end time message for each action of actions in a verification test in a target code form, to be printed into a log file of an execution of the test, so as to list chronologically the start time and end time of each of the actions in the log file. The method may also include executing the verification test to obtain the log file with the start time and end time messages and, using a processor, analyzing the log file to construct a graph representation of the validation test, based on the printed start and end times of the actions of the test.
Claims20
A method for processing verification tests for testing a design under test (DUT), the method comprising:
- for each action in a verification test, receiving from a user a message print command to print into a log file a start time of the action and a message print command to print into the log file an end time of the action, to be implanted in a target code of the verification test;
- executing the verification test to obtain the log file with the start and end times of the actions of the verification test;
- and
- using a processor, analyzing the log file to construct a directed graph representation of the verification test, based on the printed start and end times of the actions of the verification test, wherein the actions of the verification test are vertices in the directed graph, which are connected by directed edges.
A non-transitory computer readable storage medium for processing verification tests for testing a design under test (DUT), having stored thereon instructions that when executed by a processor will cause the processor to:
- for each action in a verification test, receive from a user a message print command to print into a log file a start time of the action and a message print command to print into the log file an end time of the action, to be implanted in a target code of the verification test;
- execute the verification test to obtain the log file with the start and end times of the actions of the verification test;
- and
- using a processor, analyze the log file to construct a directed graph representation of the verification test, based on the printed start and end times of said plurality of actions of the verification test, wherein the actions of the verification test are vertices in the directed graph, which are connected by directed edges.
A system for processing verification tests for testing a design under test (DUT), the system comprising:
- a memory;
- and
- a processor configured to:
- for each action in a verification test, receive from a user a message print command to print into a log file a start time of the action and a message print command to print into the log file an end time of the action, to be implanted in a target code of the verification test;
- execute the verification test to obtain the log file with the start and end times of the actions of the verification test;
- and
- analyze the log file to construct a directed graph representation of the verification test, based on the printed start and end times of said plurality of actions of the verification test, wherein the actions of the verification test are vertices in the directed graph, which are connected by directed edges.
Dependencies are inferred from the claim text.