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US 10,592,698 B2Granted
Analog-based multiple-bit chip security
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
Life of this patent
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Abstract
A semiconductor device includes a plurality of transistors on a substrate, each transistor of the plurality of transistors including a doped nanowire channel region, where the plurality of transistors are grouped into a plurality of transistor groups each including two transistors of the plurality of transistors, and where each transistor group is assigned a state based on an electrical characteristic of each transistor in each transistor group. The semiconductor device also includes a security code for the plurality of transistors generated by grouping together the states corresponding to each transistor group.
Claims20
A method for generating a security code for a semiconductor device, comprising:
- forming a plurality of transistors on a substrate, each transistor of the plurality of transistors including a channel region;
- wherein the channel region of each transistor is a portion of a nanowire;
- and
- wherein the portion of the nanowire is surrounded by a gate;
- doping the channel region of each transistor of the plurality of transistors, wherein the doping is performed with a given dopant at a given concentration;
- grouping the plurality of transistors into a plurality of transistor groups of more than one transistor;
- measuring a threshold voltage of each transistor of each transistor group;
- determining a state for each transistor group based on the measured threshold voltage of each transistor in each transistor group, wherein each state comprises a plurality of bits;
- generating the security code for the plurality of transistors by grouping together the states corresponding to each transistor group;
- wherein an effective dopant concentration of two or more of the channel regions differs based on locations of the two or more of the channel regions;
- wherein the different effective dopant concentrations of the two or more of the channel regions are represented by different bits of the plurality of bits in the security code;
- and
- concluding whether the measured threshold voltage of each transistor in each transistor group corresponds to a high threshold voltage or a low threshold voltage;
- wherein each high threshold voltage is represented by a first bit in the security code designating a high logic value, and each low threshold voltage is represented by a second bit in the security code different from the first bit and designating a low logic value.
11 more elements
A semiconductor device, comprising:
- a plurality of transistors on a substrate, each transistor of the plurality of transistors including a doped channel region;
- wherein the doped channel region of each transistor is a portion of a nanowire;
- and
- wherein the portion of the nanowire is surrounded by a gate;
- wherein the plurality of transistors are grouped into a plurality of transistor groups of more than one transistor;
- wherein each transistor group is assigned a state based on a threshold voltage of each transistor in each transistor group;
- wherein each state comprises a plurality of bits;
- and
- a security code for the plurality of transistors generated by grouping together the states corresponding to each transistor group;
- wherein an effective dopant concentration of two or more of the doped channel regions differs based on locations of the two or more of the doped channel regions;
- wherein the different effective dopant concentrations of the two or more of the doped channel regions are represented by different bits of the plurality of bits in the security code;
- wherein each state is based on whether the threshold voltage of each transistor in each transistor group corresponds to a high threshold voltage or a low threshold voltage;
- and
- wherein each high threshold voltage is represented by a first bit in the security code designating a high logic value, and each low threshold voltage is represented by a second bit in the security code different from the first bit and designating a low logic value.
11 more elements
A method for generating a security code for a semiconductor device, comprising:
- forming a plurality of transistors on a substrate, each transistor of the plurality of transistors including a nanowire channel region;
- wherein the nanowire channel region is surrounded by a gate;
- doping the nanowire channel region of each transistor of the plurality of transistors;
- wherein the doping is performed with a given dopant at a given concentration;
- grouping the plurality of transistors into a plurality of transistor groups each including two transistors of the plurality of transistors;
- measuring an electrical characteristic of each transistor of each transistor group;
- determining a state for each transistor group based on the measured electrical characteristic of each transistor in each transistor group, wherein each state comprises a plurality of bits;
- generating the security code for the plurality of transistors by grouping together the states corresponding to each transistor group;
- wherein an effective dopant concentration of two or more of the nanowire channel regions differs based on locations of the two or more of the nanowire channel regions;
- wherein the different effective dopant concentrations of the two or more of the nanowire channel regions are represented by different bits of the plurality of bits in the security code;
- and
- concluding whether the measured electrical characteristic of each transistor in each transistor group corresponds to a high electrical characteristic or a low electrical characteristic;
- wherein each high electrical characteristic is represented by a first bit in the security code designating a high logic value, and each low electrical characteristic is represented by a second bit in the security code different from the first bit and designating a low logic value.
10 more elements
A semiconductor device, comprising:
- a plurality of transistors on a substrate, each transistor of the plurality of transistors including a doped nanowire channel region;
- wherein the doped nanowire channel region is surrounded by a gate;
- and
- wherein the plurality of transistors are grouped into a plurality of transistor groups each including two transistors of the plurality of transistors;
- wherein each transistor group is assigned a state based on an electrical characteristic of each transistor in each transistor group;
- wherein each state comprises a plurality of bits;
- and
- a security code for the plurality of transistors generated by grouping together the states corresponding to each transistor group;
- wherein an effective dopant concentration of two or more of the doped nanowire channel regions differs based on locations of the two or more of the doped nanowire channel regions;
- wherein the different effective dopant concentrations of the two or more of the doped nanowire channel regions are represented by different bits of the plurality of bits in the security code;
- wherein each state is based on whether the electrical characteristic of each transistor in each transistor group corresponds to a high electrical characteristic or a low electrical characteristic;
- and
- wherein each high electrical characteristic is represented by a first bit in the security code designating a high logic value, and each low electrical characteristic is represented by a second bit in the security code different from the first bit and designating a low logic value.
10 more elements
A computer program product for generating a security code for a semiconductor device, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform a method comprising:
- grouping a plurality of transistors formed on a substrate into a plurality of transistor groups each including two transistors of the plurality of transistors;
- measuring an electrical characteristic of each transistor of each transistor group;
- determining a state for each transistor group based on the measured electrical characteristic of each transistor in each transistor group, wherein each state comprises a plurality of bits;
- generating the security code for the plurality of transistors by grouping together the states corresponding to each transistor group;
- wherein each transistor of the plurality of transistors includes a doped nanowire channel region;
- wherein the doped nanowire channel region is surrounded by a gate;
- wherein an effective dopant concentration of two or more of the doped nanowire channel regions differs based on locations of the two or more of the doped nanowire channel regions;
- wherein the different effective dopant concentrations of the two or more of the doped nanowire channel regions are represented by different bits of the plurality of bits in the security code;
- and
- concluding whether the measured electrical characteristic of each transistor in each transistor group corresponds to a high electrical characteristic or a low electrical characteristic;
- wherein each high electrical characteristic is represented by a first bit in the security code designating a high logic value, and each low electrical characteristic is represented by a second bit in the security code different from the first bit and designating a low logic value.
8 more elements
Dependencies are inferred from the claim text.