Information protection method and device based on a plurality of sub-areas for MCU chip

An information protection device based on a plurality of sub-areas the information protection device comprising:

• a micro control unit (MCU) chip being comprised of an instruction bus, a data bus, a flash controller and a user area of a flash memory storing programs, wherein the flash controller is configured to divide the user area into a plurality of sub-areas, each sub-area corresponds to a sub-area working state, respectively,
• a memory having instructions stored thereon;
• a processor configured to execute the instructions to perform operations for information protection, comprising:
• determining a preceding sub-area accessed by the instruction bus when the instruction bus accesses the user area;
• entering a preceding sub-area working state corresponding to the preceding sub-area;
• determining a current sub-area accessed by the instruction bus when the instruction bus accesses the user area;
• when the preceding sub-area is inconsistent with the current sub-area, enter a transition state;
• determining whether a duration of the transition state reaches a preset waiting time;
• when the duration of the transition state reaches the present waiting time,
• enter a current sub-area working state corresponding to the current sub-area;
• the user area comprises a plurality of reading protection levels,
• the plurality of sub-areas comprise a plurality of corresponding reading protection states;
• and when an attempt to steal the programs is made either by lowering one of the reading protection levels or exiting the reading protection state, then all the programs in the user area are erased.

A non-transitory computer readable recording medium having computer programs stored thereon for information protection based on a plurality of sub-areas

• the non-transitory computer readable recording medium further including a micro control unit (MCU) chip being comprised of an instruction bus, a data bus, a flash controller and a user area of a flash memory storing programs, wherein the flash controller is configured to divide the user area into a plurality of sub-areas, each sub-area corresponds to a sub-area working state, respectively,
• when the computer programs are executed by one or more processors of an electronic apparatus, the electronic apparatus is caused to perform:
• determining a preceding sub-area accessed by the instruction bus when the instruction bus accesses the user area;
• entering a preceding sub-area working state corresponding to the preceding sub-area;
• determining a current sub-area accessed by the instruction bus when the instruction bus accesses the user area;
• when the preceding sub-area is inconsistent with the current sub-area, enter a transition state;
• determining whether duration of the transition state reaches a preset waiting time;
• when the duration of the transition state reaches the present waiting time,
• enter a current sub-area working state corresponding to the current sub-area;
• the user area comprises a plurality of reading protection levels,
• the plurality of sub-areas comprise a plurality of corresponding reading protection states;
• and when an attempt to steal the computer programs is made either by lowering one of the reading protection levels or exiting the reading protection state, then all the computer programs in the user area are erased.