Optimizing integrated circuit designs based on interactions between multiple integration design rules

A method for optimizing integrated circuit (IC) designs based on interactions between multiple integration design rules, comprising:

• identifying, within an IC design, a plurality of IC features having design shapes;
• for each IC feature, determining a total risk value based, at least in part, on one or more integration design rules;
• ordering, based on the total risk value of each IC feature, the IC features from an IC feature having a highest total risk value to an IC feature having a lowest total risk value;
• identifying, beginning with the IC feature having the highest total risk value, a threshold count of IC features from the ordered IC features, wherein IC features within the threshold count of IC features represent a plurality of high-risk IC features;
• clipping the IC design around the high-risk features to produce a clipped area;
• simulating an overall failure rate of IC features within the clipped area;
• determining that the overall failure rate exceeds a threshold overall failure rate, and in response, calculating a predicted failure rate for each design rule that applies to IC features within the clipped area;
• identifying a high-risk design rule for which the predicted failure rate exceeds a threshold failure rate of the clipped area, wherein the high-risk design rule specifies a respective design rule value;
• and
• modifying the IC design such that a difference between the design rule value of the high-risk design rule and a corresponding design value of the IC design is reduced.