Cell-aware root cause deconvolution for defect diagnosis and yield analysis

One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:

• receiving failure reports for a plurality of integrated circuits fabricated according to a circuit design, each of the failure reports comprising test results obtained using test patterns to test one of the integrated circuits, each of the integrated circuits generating test responses different from good-machine test responses for at least one of the test patterns;
• performing logic diagnosis on the failing reports to derive a diagnosis report for each of the failing reports, the diagnosis report comprising information of suspects, the suspects comprising cell internal suspects and interconnect suspects;
• determining a probability distribution of root causes which maximizes a likelihood of observing the diagnosis reports based on a probability for each of the suspects given each of the root causes and a probability for each of the diagnosis reports given each of the suspects, each of the root causes being a physical layout feature that can cause defects, the probability for each of the suspects given each of the root causes being determined based on layout information of the circuit design, the probability for each of the diagnosis reports given each of the suspects being determined based on results of the logic diagnosis, the probability for each of the diagnosis reports given each of the cell internal suspects being weighted higher than the probability for each of the diagnosis reports given each of the interconnect suspects;
• and
• storing information of the probability distribution of the root causes.

A system, comprising:

• one or more processors, the one or more processors programmed to perform a method, the method comprising:
• receiving failure reports for a plurality of integrated circuits fabricated according to a circuit design, each of the failure reports comprising test results obtained using test patterns to test one of the integrated circuits, each of the integrated circuits generating test responses different from good-machine test responses for at least one of the test patterns;
• performing logic diagnosis on the failing reports to derive a diagnosis report for each of the failing reports, the diagnosis report comprising information of suspects, the suspects comprising cell internal suspects and interconnect suspects;
• determining a probability distribution of root causes which maximizes a likelihood of observing the diagnosis reports based on a probability for each of the suspects given each of the root causes and a probability for each of the diagnosis reports given each of the suspects, each of the root causes being a physical layout feature that can cause defects, the probability for each of the suspects given each of the root causes being determined based on layout information of the circuit design, the probability for each of the diagnosis reports given each of the suspects being determined based on results of the logic diagnosis, the probability for each of the diagnosis reports given each of the cell internal suspects being weighted higher than the probability for each of the diagnosis reports given each of the interconnect suspects;
• and
• storing information of the probability distribution of the root causes.