Assertion statement check and debug

A system comprising:

• a memory device configured to store machine-readable instructions;
• and
• a computing system including one or more processing devices, in response to executing the machine-readable instructions, configured to:
• extract sequence items from conditions in an assertion statement, wherein the assertion statement, when executed during a simulation of a circuit design, is configured to compare a simulated behavior of the circuit design against the conditions in the assertion statement;
• generate a state representation for the sequence items extracted from the assertion statement based, at least in part, on the simulated behavior of the circuit design, wherein the state representation is configured to identify states of the extracted sequence items at different clock ticks during the simulation of the circuit design;
• and
• utilize the state representation for the sequence items to determine the simulated behavior of the circuit design failed to satisfy the conditions in the assertion statement, and determine the failure of the simulated behavior to satisfy the condition in the assertion statement was due to an error included in the assertion statement.

An apparatus including a non-transitory memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

• extracting sequence items from conditions in an assertion statement, wherein the assertion statement, when executed during a simulation of a circuit design, is configured to compare a simulated behavior of the circuit design against the conditions in the assertion statement;
• generating a state representation for the sequence items extracted from the assertion statement based, at least in part, on the simulated behavior of the circuit design, wherein the state representation is configured to identify states of the extracted sequence items at different clock ticks during the simulation of the circuit design;
• and
• utilizing the state representation for the sequence items to determine the simulated behavior of the circuit design failed to satisfy the conditions in the assertion statement, and determine the failure of the simulated behavior to satisfy the condition in the assertion statement was due to an error included in the assertion statement.