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US 10,592,468 B2Granted
Shuffler circuit for lane shuffle in SIMD architecture
AssigneeQUALCOMM Incorporated
InventorsLiang Han, Xiangdong Jin, Lin Chen, Yun Du, Alexei Vladimirovich Bourd
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Abstract
Techniques are described to perform a shuffle operation. Rather than using an all-lane to all-lane cross bar, a shuffler circuit having a smaller cross bar is described. The shuffler circuit performs the shuffle operation piecewise by reordering data received from processing lanes and outputting the reordered data.
Claims23
A device for processing data, the device comprising:
- a plurality of processing lanes, each of the processing lanes comprising circuitry to process the data, wherein the processing lanes are configured in a single instruction multiple data (SIMD) structure, and wherein the processing lanes are grouped into a plurality of banks, each bank of the plurality of banks comprises one or more processing lanes of the plurality of processing lanes;
- and
- a shuffler circuit comprising a plurality of input ports and a plurality of output ports, wherein each output port of the plurality of output ports is configured to output to only one processing lane in each bank of the plurality of banks, and wherein the shuffler circuit is configured to:
- in a first iteration, receive data, on the input ports, including entire scalar or vector values from each processing lane of only a source subset of the processing lanes, wherein the source subset of the processing lanes is fewer processing lanes than the plurality of processing lanes, wherein a first processing lane of the source subset of the processing lanes is associated with first data, wherein a second processing lane of the source subset of the processing lanes is associated with second data, and wherein an order of the data is based on relative positions of the first processing lane and the second processing lane in a bank of the plurality of banks that includes the first processing lane and the second processing lane such that in the order of the data the second data follows the first data;
- in the first iteration, reorder the data including the entire scalar or vector values received from the source subset of the processing lanes responsive to an instruction instructing each of the processing lanes to output data to another one of the processing lanes based on the relative positions of the first and second processing lanes and the instruction instructing to which processing lanes each of the processing lanes are to output data such that the second data does not follow the first data and the second data is in the reordered data;
- and
- in the first iteration, output the reordered data including the entire scalar or vector values respectively to all of the processing lanes, wherein a destination subset of the processing lanes stores the reordered data in corresponding registers, wherein the destination subset of the processing lanes is fewer than the plurality of processing lanes, wherein processing lanes other than the destination subset of the processing lanes discard the reordered data that is received by the processing lanes other than the destination subset of the processing lanes, wherein to output the reordered data, the shuffler circuit is configured to output the reordered data to each of the plurality of banks, and wherein to output the reordered data to each of the plurality of banks, each output port of the plurality of output ports only outputs to respective processing lanes of each bank of the plurality of banks,
- wherein the shuffler circuit is further configured to:
- in each iteration of multiple iterations following the first iteration, receive data from only a successive source subset of the processing lanes;
- in each iteration of the multiple iterations, reorder the data received from the successive source subset of the processing lanes to generate successive reordered data responsive to the instruction instructing each of the processing lanes to output data to another one of the processing lanes;
- and
- in each iteration of the multiple iterations, output the successive reordered data to all of the processing lanes, and wherein successive destination subsets of the processing lanes store the successive reordered data in corresponding registers.
9 more elements
A method of processing data, the method comprising:
- in a first iteration, receiving, with input ports of a shuffler circuit, data including entire scalar or vector values from each processing lane of only a source subset of processing lanes of a plurality of processing lanes, each of the processing lanes comprising circuitry to process the data, wherein the processing lanes are configured in a single instruction multiple data (SIMD) structure, wherein the processing lanes are grouped into a plurality of banks, each bank of the plurality of banks comprises one or more processing lanes of the plurality of processing lanes, wherein the source subset of the processing lanes is fewer processing lanes than the plurality of processing lanes, wherein a first processing lane of the source subset of the processing lanes is associated with first data, wherein a second processing lane of the source subset of the processing lanes is associated with second data, and wherein an order of the data is based on relative positions of the first processing lane and the second processing lane in a bank of the plurality of banks that includes the first processing lane and the second processing lane such that in the order of the data the second data follows the first data;
- in the first iteration, reordering, with the shuffler circuit, the data including the entire scalar or vector values received from the source subset of the processing lanes responsive to an instruction instructing each of the processing lanes to output data to another one of the processing lanes based on the relative positions of the first and second processing lanes and the instruction instructing to which processing lanes each of the processing lanes are to output data such that the second data does not follow the first data and the second data is in the reordered data;
- and
- in the first iteration, outputting, with a plurality output ports of the shuffler circuit, the reordered data including the entire scalar or vector values respectively to all of the processing lanes, wherein each output port of the plurality of output ports is configured to output to only one processing lane in each bank of the plurality of banks, wherein a destination subset of the processing lanes stores the reordered data in corresponding registers, wherein the destination subset of the processing lanes is fewer than the plurality of processing lanes, wherein processing lanes other than the destination subset of the processing lanes discard the reordered data that is received by the processing lanes other than the destination subset of the processing lanes, wherein outputting the reordered data comprises outputting the reordered data to each of the plurality of banks, and wherein outputting the reordered data to each of the plurality of banks comprises each output port of the plurality of output ports only outputting to respective processing lanes of each bank of the plurality of banks,
- the method further comprising:
- in each iteration of multiple iterations following the first iteration, receiving data from only a successive source subset of the processing lanes;
- in each iteration of the multiple iterations, reordering the data received from the successive source subset of the processing lanes to generate successive reordered data responsive to the instruction instructing each of the processing lanes to output data to another one of the processing lanes;
- and
- in each iteration of the multiple iterations, outputting the successive reordered data to all of the processing lanes, and wherein successive destination subsets of the processing lanes store the successive reordered data in corresponding registers.
6 more elements
A device for processing data, the device comprising:
- means for receiving, in a first iteration, data, via input porst, including entire scalar or vector values from each processing lane of only a source subset of processing lanes of a plurality of processing lanes, each of the processing lanes comprising circuitry to process the data, wherein the processing lanes are configured in a single instruction multiple data (SIMD) structure, wherein the processing lanes are grouped into a plurality of banks, each bank of the plurality of banks comprises one or more processing lanes of the plurality of processing lanes, wherein the source subset of processing lanes is fewer processing lanes than the plurality of processing lanes, wherein a first processing lane of the source subset of the processing lanes is associated with first data, wherein a second processing lane of the source subset of the processing lanes is associated with second data, and wherein an order of the data is based on relative positions of the first processing lane and the second processing lane in a bank of the plurality of banks that includes the first processing lane and the second processing lane such that in the order of the data the second data follows the first data;
- means for reordering, in the first iteration, the data including the entire scalar or vector values received from the source subset of the processing lanes responsive to an instruction instructing each of the processing lanes to output data to another one of the processing lanes based on the relative positions of the first and second processing lanes and the instruction instructing to which processing lanes each of the processing lanes are to output data such that the second data does not follow the first data and the second data is in the reordered data;
- and
- means for outputting, in the first iteration, the reordered data, with a plurality of ports, including the entire scalar or vector values respectively to all of the processing lanes, wherein each output port of the plurality of output ports is configured to output to only one processing lane in each bank of the plurality of banks, wherein a destination subset of the processing lanes stores the reordered data in corresponding registers, wherein the destination subset of the processing lanes is fewer than the plurality of processing lanes, wherein processing lanes other than the destination subset of the processing lanes discard the reordered data that is received by the processing lanes other than the destination subset of the processing lanes, wherein the means for outputting the reordered data comprises means for outputting the reordered data to each of the plurality of banks, and wherein the means for outputting the reordered data to each of the plurality of banks comprises means for each output port of the plurality of output ports only outputting to respective processing lanes of each bank of the plurality of banks,
- the device further comprising:
- means for receiving, in each iteration of multiple iterations following the first iteration, data from only a successive source subset of the processing lanes;
- means for reordering, in each iteration of the multiple iterations following the first iteration, the data received from the successive source subset of the processing lanes to generate successive reordered data responsive to the instruction instructing each of the processing lanes to output data to another one of the processing lanes;
- and
- means for outputting, in each iteration of the multiple iterations following the first iteration, the successive reordered data to all of the processing lanes, and wherein successive destination subsets of the processing lanes store the successive reordered data in corresponding registers.
6 more elements
A computer-readable storage medium comprising instructions that when executed cause a shuffler circuit of a device for processing data to:
- in a first iteration, receive, with input ports of the shuffler circuit, data including entire scalar or vector values from each processing lane of only a source subset of processing lanes of a plurality of processing lanes, each of the processing lanes comprising circuitry to process the data, wherein the processing lanes are configured in a single instruction multiple data (SIMD) structure, wherein the processing lanes are grouped into a plurality of banks, each bank of the plurality of banks comprises one or more processing lanes of the plurality of processing lanes, wherein the source subset of the processing lanes is fewer processing lanes than the plurality of processing lanes, wherein a first processing lane of the source subset of the processing lanes is associated with first data, wherein a second processing lane of the source subset of the processing lanes is associated with second data, and wherein an order of the data is based on relative positions of the first processing lane and the second processing lane in a bank of the plurality of banks that includes the first processing lane and the second processing lane such that in the order of the data the second data follows the first data;
- in the first iteration, reorder the data including the entire scalar or vector values received from the source subset of the processing lanes responsive to an instruction instructing each of the processing lanes to output data to another one of the processing lanes based on the relative positions of the first and second processing lanes and the instruction instructing to which processing lanes each of the processing lanes are to output data such that the second data does not follow the first data and the second data is in the reordered data;
- and
- in the first iteration, output, with a plurality of output ports of the shuffler circuit, the reordered data including the entire scalar or vector values respectively to all of the processing lanes, wherein each output port of the plurality of output ports is configured to output to only one processing lane in each bank of the plurality of banks, wherein a destination subset of the processing lanes stores the reordered data in corresponding registers, wherein the destination subset of the processing lanes is fewer than the plurality of processing lanes, wherein processing lanes other than the destination subset of the processing lanes discard the reordered data that is received by the processing lanes other than the destination subset of the processing lanes, wherein the instructions that cause the shuffler circuit to output the reordered data comprise instructions that cause the shuffler circuit to output the reordered data to each of the plurality of banks, and wherein the instructions that cause the shuffler circuit o output the reordered data to each of the plurality of banks comprises instructions that cause each output port of the plurality of output ports to only output to respective processing lanes of each bank of the plurality of banks,
- the instructions further comprising instructions that cause the shuffler circuit to:
- in each iteration of multiple iterations following the first iteration, receive data from only a successive source subset of the processing lanes;
- in each iteration of the multiple iterations, reorder the data received from the successive source subset of the processing lanes to generate successive reordered data responsive to the instruction instructing each of the processing lanes to output data to another one of the processing lanes;
- and
- in each iteration of the multiple iterations, output the successive reordered data to all of the processing lanes, and wherein successive destination subsets of the processing lanes store the successive reordered data in corresponding registers.
6 more elements
Dependencies are inferred from the claim text.