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US 10,592,466 B2Granted
Graphic processor unit providing reduced storage costs for similar operands
AssigneeWisconsin Alumni Research Foundation
InventorsNam Sung Kim, Zhenhong Liu
Life of this patent
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Abstract
A GPU architecture employs a crossbar switch to preferentially store operand vectors in a compressed form allowing reduction in the number of memory circuits that must be activated during an operand fetch and to allow existing execution units to be used for scalar execution. Scalar execution can be performed during branch divergence.
Claims19
A computer architecture comprising:
- a register file holding vector registers of operands in different memory circuits;
- a set of execution units for SIMT execution of an instruction in parallel using a set of operands;
- and
- scalar execution circuitry evaluating operands of a set of operands subject to a read request by the execution units, and when all operands of the set of operands are identical;
- (i) transferring only a representative operand of the set of operands to a single execution unit without activating memory circuits for each of the operands of the set of operands;
- (ii) executing an operation on the representative operand on the single execution unit while holding other execution units idle;
- and
- (iii) storing a result of the execution of the representative operand as a single operand without activating memory circuits for each of the operands of the set of operands;
- wherein the scalar execution circuitry further:
- (iv) evaluates operands being written to the register file across a set of operands to identify identical and non-identical portions of those operands of the set of operands and sorts any non-identical portions preferentially into one memory circuit using a crossbar switch and separately sorts a representative identical portion into a storage location different from the one memory circuit;
- (v) in response to a request for reading a set of operands by the execution units from the register file where those operands include sorted non-identical portions, activates a memory circuit holding the sorted non-identical portions and not all of the memory circuits holding the set of operands and combining each sorted non-identical portion with the representative portion to provide reconstructed operands;
- and
- (vi) provides the reconstructed operands to multiple of the execution units.
10 more elements
A computer architecture comprising:
- a register file holding vector registers of multiple operands in different memory circuits;
- a set of execution units for SIMT execution of an instruction in parallel using a set of operands;
- a crossbar switch providing a parallel connection of banks of the register file to execution units according to a crossbar switch command permitting connection of a vector register to any execution unit;
- and
- scalar execution circuitry:
- (i) evaluating operands being written to the register file across a set of operands to identify identical and non-identical portions of those operands of the set of operands and controlling the crossbar switch to route any non-identical portions preferentially into one memory circuit and sort a representative identical portion into a storage location different from the one memory circuit;
- and
- (ii) in response to a request for reading a set of operands by the execution units from the register file where those operands include routed non-identical portions, activate a memory circuit holding the routed non-identical portions and combining each routed non-identical portion with the representative portion to provide reconstructed operands to multiple of the execution units.
5 more elements
A method of executing programs on a computer architecture having:
- a register file holding vector registers of operands in different memory circuits;
- a set of execution units for SIMT execution of an instruction in parallel using a set of operands;
- scalar execution circuitry evaluating operands of a set of operands subject to a read request by the execution units, and when all operands of the set of operands are identical:
- (i) transferring only a representative operand of the set of operands to a single execution unit without activating memory circuits for each of the operands of the set of operands;
- (ii) executing the representative operand on the single execution unit while holding other execution units idle;
- and
- (iii) storing a result of execution of the representative operand as a single operand without activating memory circuits for each of the operands of the set of operands;
- the method comprising, when operands subject to a read request by execution units are identical, the steps of:
- (a) transferring only a representative operand of the set of operands to a single execution unit without activating memory circuits for each of the operands of the set of operands;
- (b) executing the representative operand on the single execution unit while holding other execution units idle;
- and
- (c) storing a result of execution of the representative operand as a single operand without activating memory circuits for each of the operands of the set of operands;
- and
- further including the steps of:
- (d) evaluating operands being written to the register file across a set of operands to identify, identical and non-identical portions of those operands of the set of operands and sorts any non-identical portions preferentially into one memory circuit using a crossbar switch and sorts a representative identical portion into a storage location different from the one memory circuit;
- (e) in response to a request for reading a set of operands by the execution units from the register file where those operands include sorted non-identical portions, activating a memory circuit holding the sorted non-identical portions and not all of the memory circuits holding the set of operands and combining each sorted non-identical portion with the representative portion to provide reconstructed operands;
- and
- (f) providing the reconstructed operands to multiple of the execution units.
15 more elements
Dependencies are inferred from the claim text.