US 10,592,460 B2 · Apparatus for virtual channel allocation via a high speed bus interface

Abstract

Methods and apparatus for virtual channel allocation within an electronic device. In one exemplary embodiment, the device is a consumer electronics device having multiple camera sensors uses a modified high-speed protocol (e.g., DisplayPort Multi-Stream Transport (MST) protocol) to process camera data via one or more virtual channels. Unlike traditional solutions which rely on an intelligent source device to manage a network of devices, the present disclosure describes in one aspect a network of nodes internal to a consumer electronic device that is managed by the sink node (i.e., a “smart sink”). Additionally, since the full suite of protocol (e.g., DisplayPort) capabilities are unnecessary for certain design scenarios, certain further disclosed simplifications improve performance for sink nodes having very modest capabilities.

Claims20

Dependent claims

A sink device of a media apparatus, the sink device being configured to:

instruct a sensor device of the media apparatus to update a payload allocation table associated with the sensor device via an auxiliary channel;
in response to a determination that the payload allocation table associated with the sensor device has been updated, instruct the sensor device, via the auxiliary channel, to send an allocation change trigger via a transport channel;
and
upon receipt of the allocation change trigger from the sensor device, instruct the sensor device to initiate data transmission.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

16/241,781Filed 7 Jan 2019 · continuation

Priority

10 Dec 2013

Published

US 2019/0243798 A18 Aug 2019

Granted

17 Mar 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification18 codes

G06F 13/426
On a daisy chain bus: using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
G06F 13/4282
Bus transfer protocol, e.g. handshake; Synchronisation: on a serial bus, e.g. I2C bus, SPI bus
G09G 5/00
Control arrangements or circuits for visual indicators common to cathode-ray tube indicators
G09G 5/006
Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto: details of…

Family

Application61/914,322Us provisional application · filed 10 Dec 2013

Application14/566,454Parent of this division · filed 10 Dec 2014

Application15/894,719Parent of this continuation · filed 12 Feb 2018

US 9,892,084 B2Parent of this division · filed 13 Feb 2018

US 10,176,141 B2Parent of this continuation · filed 8 Jan 2019

US 2019/0243798 A1Pre-grant publication · published 8 Aug 2019

Application15/894,719Parent of this division

US 2015/0205749 A1Published application

US 2018/0232333 A1Published application

US 10,592,460 B2This patent

From the US filing history. Foreign family members aren’t listed.

Apparatus for virtual channel allocation via a high speed bus interface

Life of this patent

Apparatus for virtual channel allocation via a high speed bus interface

Life of this patent

Abstract

Claims20