Low latency interconnect protocol for coherent multi-chip communication

A system comprising:

• a first system-on-chip (SOC) including a first set of input/output (I/O) ports, a first cache, and a first plurality of processors, the first SOC configured to generate a data message;
• a second SOC including a second set of I/O ports, a second cache, and a second plurality of processors, each of the second set of I/O ports connected to a respective port of the first set of I/O ports via a bus;
• the first SOC including an interface configured to 1) generate a stream of data words from the data message, the data words alternating between even data words and odd data words;
• 2) divide each data word in the stream of data words into a first pattern of slices for even data words and a second pattern of slices for odd data words, and distribute the slices across the first set of I/O ports;
• 3) at each of the first set of I/O ports,
• i) group two slices from two successive cycles and encode the grouped slices;
• and
• ii) generate a plurality of metaframes from encoded grouped slices;
• and
• 4) transmit the plurality of metaframes for each of the first set of I/O ports to the second SOC.