Custom compute cores in integrated circuit devices

An integrated circuit device comprising:

• one or more custom compute cores configured to perform at least one preprocessing function on an input data stream from a processor to generate a preprocessed input data stream, perform at least one post-processing function on one or more event vectors read from one or more state machine engines of a first chip, or both, wherein:
• the one or more custom compute cores are implemented in fabric resources of the integrated circuit device;
• and
• the one or more state machine engines of the first chip are each configured to analyze the preprocessed input data stream based on configuration data and to output the one or more event vectors as a result of the analysis, wherein the one or more state machine engines of the first chip are physically separate from and coupled to the integrated circuit device as a second chip.

A device comprising:

• a first chip comprising a state machine engine comprising one or more data analysis circuits each configured to analyze input data based on configuration data and to output result data of the analysis;
• and
• a second chip as an integrated circuit device physically separate from and coupled to the state machine engine of the first chip, the integrated circuit device comprising:
• one or more custom compute cores implemented in fabric resources of the integrated circuit device, wherein the one or more custom compute cores are configured to perform preprocessing functionality on the input data prior to a direct memory access (DMA) engine writing the input data to the one or more data analysis circuits, post-processing functionality on the result data after the result data is read from the one or more data analysis circuits, or both.

A method comprising:

• receiving a data stream of symbols to be searched at a first chip as an integrated circuit device from a processor;
• performing one or more preprocessing functions on the data stream to generate a preprocessed data stream using one or more preprocessing cores of the integrated circuit device;
• outputting the preprocessed data stream to a second chip comprising one or more state machine engines physically separate from and coupled to the integrated circuit device as the first chip, wherein the one or more state machine engines search the preprocessed data stream to generate one or more event vectors;
• receiving the one or more event vectors at the integrated circuit device from the one or more state machine engines;
• performing one or more post-processing functions on the one or more event vectors to generate one or more post-processed event vectors using one or more post-processing cores of the integrated circuit device;
• and
• outputting the one or more post-processed event vectors to the processor.