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US 10,592,445 B2Granted
Techniques to access or operate a dual in-line memory module via multiple data channels
AssigneeIntel Corporation
InventorsBill Nale, Christopher E. Cox, Kuljit S. Bains, George Vergis, James A. McCall, Chong J. Zhao, Suneeta Sah, Pete D. Vogt, John R. Goles
Life of this patent
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Abstract
Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.
Claims31
An apparatus comprising:
- an interface;
- and
- a memory controller that includes circuitry to:
- receive a request to access one or more memory devices maintained at a dual in-line memory module (DIMM);
- send, responsive to the request, bits of a first control address command (CAC) to access the one or more memory devices through the interface via a first data channel from among a plurality of data channels coupled with the DIMM, the bits of the first CAC routed through a command address bus of the first data channel, wherein a first half of the bits of the first CAC are routed through the command address bus of the first data channel at a high portion of a first clock signal and a second half of the bits of the first CAC are routed through the command address bus of the first data channel at a low portion of the first clock signal;
- and
- access the one or more memory devices via the first data channel to fulfill the request.
4 more elements
A method comprising:
- receiving, at a processor circuit, a request to access one or more memory devices maintained at a dual in-line memory module (DIMM);
- sending, responsive to the request, bits of a first control address command (CAC) to access the one or more memory devices through the interface via a first data channel from among a plurality of data channels coupled with the DIMM, the bits of the first CAC routed through a command address bus of the first data channel, wherein a first half of the bits of the first CAC are routed through the command address bus of the first data channel at a high portion of a first clock signal and a second half of the bits of the first CAC are routed through the command address bus of the first data channel at a low portion of the first clock signal;
- and
- accessing the one or more memory devices via the first data channel to fulfill the request.
1 more element
A system comprising:
- at least one processor for a computing device to execute one or more applications;
- a memory controller coupled with the at least one processor, the memory controller including circuitry to:
- receive a request from an application from among the one or more applications to access one or more memory devices maintained at a dual in-line memory module (DIMM);
- sending, responsive to the request, bits of a first control address command (CAC) to access the one or more memory devices through the interface via a first data channel from among a plurality of data channels coupled with the DIMM, the bits of the first CAC routed through a command address bus of the first data channel, wherein a first half of the bits of the first CAC are routed through the command address bus of the first data channel at a high portion of a first clock signal and a second half of the bits of the first CAC are routed through the command address bus of the first data channel at a low portion of the first clock signal;
- and
- access the one or more memory devices via the first data channel to fulfill the request.
3 more elements
An apparatus comprising:
- a dual in-line memory module (DIMM) including a first plurality of memory devices on a first side and a second plurality of memory devices on a second side;
- a command address bus of a first data channel to receive bits of a first control address command (CAC) to access one or more memory devices of the first plurality of memory devices via the first data channel, wherein a first half of the bits of the first CAC are received through the command address bus of the first data channel at a high portion of a first clock signal and a second half of the bits of the first CAC are received through the command address bus of the first data channel at a low portion of the first clock signal;
- and
- a command bus of a second data channel to receive bits of a second CAC to access one or more memory devices of the second plurality of memory devices via the second data channel, wherein a first half of the bits of the second CAC are received through the command address bus of the second data channel at a high portion of a second clock signal and a second half of the bits of the second CAC are receive through the command address bus of the second data channel at a low portion of the second clock signal.
1 more element
Dependencies are inferred from the claim text.