Reconfigurable interconnected programmable processors

A processor-implemented method for assembling an apparatus for processing comprising:

• including a plurality of software programmable processors controlled by rotating circular buffers, wherein:
• a first processor and a second processor within the plurality of software programmable processors are individually programmable;
• the first processor further comprises an arithmetic logic unit controlled by a circular buffer;
• and
• the circular buffer provides for dynamic programming of the arithmetic logic unit;
• coupling the first processor within the plurality of software programmable processors to neighbor processors within the plurality of software programmable processors;
• sending and receiving, by the first processor, data from the neighbor processors;
• configuring the first processor and the second processor to operate on a common instruction cycle;
• and
• coupling an output of the first processor from a first instruction cycle to an input to the second processor on a subsequent instruction cycle, wherein the subsequent instruction cycle is an immediately subsequent instruction cycle.

A computer program product embodied in a non-transitory computer readable medium for implementation of a computation apparatus comprising code for designing a data manipulation architecture including:

• a plurality of software programmable processors controlled by rotating circular buffers wherein:
• a first processor and a second processor within the plurality of software programmable processors are individually programmable;
• the first processor further comprises an arithmetic logic unit controlled by a circular buffer;
• the circular buffer provides for dynamic programming of the arithmetic logic unit;
• the first processor within the plurality of software programmable processors is coupled to neighbor processors within the plurality of software programmable processors;
• the first processor sends and receives data from the neighbor processors;
• the first processor and the second processor are configured to operate on a common instruction cycle;
• and
• an output of the first processor from a first instruction cycle is an input to the second processor on a subsequent instruction cycle, wherein the subsequent instruction cycle is an immediately subsequent instruction cycle.