Asynchronous buffer with pointer offsets
AssigneeAdvanced Micro Devices, Inc.
InventorsRichard Martin Born, David M. Dahle, Steven Kommrusch
Life of this patent
Estimating the term…
Abstract
A processor applies offset values to read and write pointers to a first-in-first-out buffer (FIFO) for data being transferred between clock domains. The pointer offsets are based on a frequency ratio between the clock domains, and reduce latency while ensuring that data is not read by the receiving clock domain from an entry of the FIFO until after the data has been written to the entry, thereby reducing data transfer errors. The processor resets the pointer offset values in response to a change in clock frequency at one or both of the clock domains, allowing the processor to continue to accurately transfer data in response to clock frequency changes.
Claims20
A method comprising:
- at a first clock domain of a processor, incrementing a position of a write pointer with respect to a plurality of entries of a buffer based on a depth of the buffer and a first offset value;
- accessing, at a write module of the processor, a first entry of the plurality of entries of the buffer in response to the write pointer indicating the first entry;
- at a second clock domain of the processor, incrementing a position of a read pointer with respect to the plurality of entries of the buffer based on the position of the write pointer and a second offset value, the second offset value based on a ratio of a first frequency of a first clock signal of the first clock domain to a second frequency of a second clock signal of the second clock domain, the second clock signal asynchronous with the first clock signal;
- and
- accessing, at a read module of the processor, the first entry of the plurality of entries of the buffer in response to the read pointer indicating the first entry.
A method, comprising:
- at a first clock domain of a processor, offsetting a position of a write pointer with respect to a first-in first-out buffer (FIFO) having a depth, based on a first offset value;
- at a second clock domain of the processor, offsetting a position of a read pointer with respect to the FIFO based on a second offset value, wherein the second offset value is based on a ratio of a first period of a first clock signal of the first clock domain to a second period of a second clock signal of the second clock domain;
- accessing, at a write module of the processor, a first entry of the FIFO based on the position of the write pointer;
- incrementing the write pointer with respect to the FIFO in response to accessing the first entry;
- reading, at a read module of the processor, from the first entry of the FIFO based on the position of the read pointer with respect to the FIFO;
- and
- incrementing the read pointer with respect to the FIFO in response to reading from the first entry.
A processor, comprising:
- a first-in first-out buffer (FIFO);
- a first clock domain comprising:
- a write pointer;
- a first synchronizer;
- and
- a write module configured to access a first entry of the FIFO in response to a position of the write pointer with respect to the FIFO, wherein the position of the write pointer is based on a depth of the FIFO and a first offset value;
- a second clock domain comprising:
- a read pointer;
- a second synchronizer;
- and
- a read module configured to access the first entry of the FIFO in response to a position of the read pointer with respect to the FIFO, wherein the position of the read pointer is based on the position of the write pointer and a second offset value;
- and
- a controller configured to determine the first offset value and the second offset value.
Dependencies are inferred from the claim text.