System and method for filtering field programmable gate array input/output

A system comprising:

• a processor;
• a Field Programmable Gate Array (FPGA);
• and
• a computer-readable storage medium having instructions stored which, when executed by the processor, cause the processor to perform operations comprising:
• receiving a FPGA program bit stream;
• generating, based at least in part on the FPGA bit stream, a plurality of FPGA programming logic segments;
• modifying, based at least in part on the FPGA programming logic segments, an FPGA to comprise a core logic layer and a filtering layer, wherein the filtering layer comprises a first set of logic blocks within the FPGA and the core logic layer comprises a second set of logic blocks within the FPGA, the first set of logic blocks being distinct from the second set of logic blocks;
• receiving a first input associated with the core logic layer, wherein the first input is one or more predefined inputs;
• and
• in response to determining that the first input is one or more of the predefined inputs:
• storing an indication of the first input and a timestamp associated with the first input;
• modifying the first input to prevent the first input from being received by the core logic layer;
• and
• output the indication of the first input to a display.

A computer-readable storage device having instructions stored which, when executed by a computing device, cause the computing device to perform operations comprising:

• receiving a Field Programmable Gate Array (FPGA) program bit stream;
• generating, based at least in part on the FPGA bit stream, a plurality of FPGA programming logic segments;
• modifying, based at least in part on the FPGA programming logic segments, an FPGA to comprise a core logic layer and a filtering layer, wherein the filtering layer comprises a first set of logic blocks within the FPGA and the core logic layer comprises a second set of logic blocks within the FPGA, the first set of logic blocks being distinct from the second set of logic blocks;
• receiving a first input associated with the core logic layer, wherein the first input is one or more predefined inputs;
• and
• in response to determining that the first input is one or more of the predefined inputs:
• storing an indication of the first input and a timestamp associated with the first input;
• modifying the first input to prevent the first input from being received by the core logic layer;
• and
• outputting the indication of the first input to a display.